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White Papers > Wafer Processing

Enhancing process control flexibility for sub-90nm applications

01 March 2005 | Edition 25, Wafer Processing
John Yamartino, Vivien Chang, James Holland & Andrey Poliektov, Applied Materials, Inc., Santa Clara, CA, USA Read more >>

Copper interconnects with CVD low-k BEOL dielectric and their reliability

01 March 2005 | Edition 25, Wafer Processing
H. S. Rathore, D. B. Nguyen, B. Agarwala, K. Chanda, R. G. Filippi, D. Edelstein, C. C. Yang, A. Cowley,W. Landers, M. Yoon, L. Clevenger, J. Demarest, C. R. Davis & C. A. Barile, IBM Systems and Technology Group, Hopewell Junction, NY, USA, C. K. Hu, IBM T. J.Watson Research Center, Yorktown Heights, NY, USA, F. Chen, IBM Systems and Technology Group, Essex Junction, VT, USA, D. Hawken, IBM Systems and Technology Group, Endicott, NY, USA Read more >>

A global low power design solution

01 March 2005 | Edition 25, Wafer Processing
François Thomas, Field Marketing Director, Cadence Europe IC, Velizy, France Read more >>

E=MC3 a review of copper annealing processes and equipment

01 December 2004 | Edition 24, Wafer Processing
Ken Sautter, KMS Enterprises, Stuart Allen & Bill Moffat, Yield Engineering Systems Inc., San Jose, CA, USA Read more >>

Development of multi-levelinterconnect technologies for 2nd generation 65nm node VLSIs

01 December 2004 | Edition 24, Wafer Processing
Yoshihiro Hayashi, System Devices Research Laboratories, NEC Read more >>

Breakthrough technology for CMP

01 December 2004 | Edition 24, Wafer Processing
Dr. Liang Chen, General Manager, CMP Division, PPC Product Business Group, Applied Materials Inc, USA Read more >>

Advanced gate electrodes for future generation CMOS

01 December 2004 | Edition 24, Wafer Processing
Prashant Majhi, (Assignment from: Philips Semiconductors), Huang-Chun Wen, Gennadi Bersuker, George Brown, Byoung-Hun Lee, (Assignment from: IBM), & H. Huff, SEMATECH, Austin, Texas, USA Read more >>

Advanced CMP consumable design for defectivity control

01 December 2004 | Edition 24, Wafer Processing
Halbert Tam, JSR Micro, Inc., Sunnyvale, CA, USA & Nobuo Kawahashi, JSR Corporation, Yokkaichi, Japan Read more >>

Investigation of the fast removal of nano PSL and submicron silica and silicon nitride particles

01 August 2004 | Edition 23, Wafer Processing
John Michael Bernard, Oytun Guldkin & Ahmed Busnaina, NSF Center for Nano and Micro Contamination Control, Northeastern University, Boston, MA, USA Jingoo Park, Hanyang University, Ansan, Korea Read more >>

High-k/metal gate transistor scaling and device concerns for advanced CMOS device applications

01 August 2004 | Edition 23, Wafer Processing
Mark I. Gardnera, Sundar Gopalan, Jim Gutt, Paul Kirschb, Siddarth Kirshnan, Jeff Petersonc, Hong-Jyh Lid & Howard R. Huff, International SEMATECH, Austin, Texas, USA Assignment from: a Advanced Micro Devices, b IBM, c Intel d Infineon Read more >>