Online information source for semiconductor professionals

White Papers > Wafer Processing

Full copper electrochemical mechanical planarization (Ecmp) as a technology enabler for the 45nm

01 September 2007 | Edition 35, Wafer Processing | Comments (2)
M. Mellier, T. Berger, R. Duru, O. Hinsinger & G. Wyborn, STMicroelectronics, France; M. Rivoire, CEA–LETI, France & K-L. Chang, Y. Wang, V. Ripoche, S. Tsai & M. Thothadri, Applied Materials, USA Read more >>

External resistance: a paradigm shift in approaching strain engineering

01 September 2007 | Edition 35, Wafer Processing
R. Arghavani, A. M. Noori, A. Gelatos, A. Khandelwal, S. Gandikota &
S. Felch, Applied Materials, California, USA, & S. E. Thompson, University of Florida, USA Read more >>

Defect monitoring on memory devices using broadband brightfield inspection

01 September 2007 | Edition 35, Wafer Processing
Uwe Seifert & Carlos Mata, Qimonda AG, Dresden, Germany; Thomas Trautzsch & Martin Tuckermann, KLA-Tencor GmbH, Dresden, Germany; Aneesh Khullar, Jorge Fernandez & Catherine Perry-Sullivan, KLA-Tencor Corporation, California, USA
Read more >>

Plasma-induced low-k modification and its impact on reliability.

01 September 2007 | Edition 35, Wafer Processing
By Zsolt TÅ?kei, Mikhail Baklanov, Ivan Ciofi, Yunlong Li & Adam Urbanowicz, IMEC, Leuven, Belgium Read more >>

Infrared metrology for shallow recess structures in deep trench DRAM

01 September 2007 | Edition 35, Wafer Processing
By Michael Gostein, John Byrnes, Alex Mazurenko & Tony Bonanno, Advanced Metrology Systems; Peter Weidner & Alexander Kasic, Qimonda Dresden, Germany;
Philip Abromitis, Qimonda Richmond, USA
Read more >>

Study of Ni-silicide contacts to Si:C source/drain

01 June 2007 | Edition 34, Wafer Processing
Y. Chob, F. Nourib, R. Schreutelkamp & Y. Kim, Applied Materials Inc., CA, USA, &
S. Mertens, P. Verheyen, J. Steenbergen, C. Vrancken, O. Richard, Z. Tökei, A. Lauwers, H. Bender, B. Van Daele, W. Vandervorst, L. Geenen, P. Absil, S. Kubicek & C. Demeurisse, IMEC, Leuven, Belgium Read more >>

SPM techniques for carrier profiling at advanced technology nodes

01 June 2007 | Edition 34, Wafer Processing
Vito Raineri, Filippo Giannazzo, CNR-IMM, Catania, Italy, & Raffaele Mucciato, 2M Strumenti, Roma, Italy Read more >>

Sidewall metrology technologies for 32nm node and beyond

01 June 2007 | Edition 34, Wafer Processing
Johann Foucher, CEA/LETI-MINATEC, France Read more >>

Immersion photoresist qualification

01 June 2007 | Edition 34, Wafer Processing
Monique Ercken, Roel Gronheid, Ivan Pollentier & Philippe Leray, IMEC, Leuven, Belgium Read more >>

Ready for a scalable phase change?

01 April 2007 | Edition 33, Wafer Processing
Dr Mike Cooke, technology journalist, London, UK Read more >>