Online information source for semiconductor professionals

White Papers > Wafer Processing

PREVIEW: Edition 39: Wafer-edge yield engineering in leading-edge DRAM manufacturing

12 March 2009 | Edition 39, Wafer Processing

FT 39By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper.


Edition 38: CMOS 32nm technology node: business as usual for interconnect damascene patterning?

15 January 2009 | Edition 38, Wafer Processing
FT38By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Read more >>

Edition 38: Metrology equipment for the 45-32nm nodes

11 December 2008 | Edition 38, Wafer Processing
FT38For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Read more >>

Advanced process control of copper electroplating thickness profile

Sai Boyapati, Kevin Chamness, Frank Smith, Patrick Cowan & John Crowley, Spansion, Inc., Austin, Texas, USA Read more >>

Meeting the doping challenges: the case for plasma doping

01 March 2008 | Edition 37, Wafer Processing
Jose I. Del Agua, Tze Poon, Pete Porshnev $ Majeed Foad, Applied Materials, Inc., Santa Clara, California; Malgorzata Jurczak, Jean-Luc Everaert & Wilfrid Vandervorst, IMEC, Leuven, Belgium Read more >>

Contamination control for the 32nm node

01 March 2008 | Edition 37, Wafer Processing
Twan Bearda, Rita Vos, Paul W. Mertens, Gabriela Catana & Cedric Huyghebaert, IMEC, Leuven, Belgium Read more >>

ALD developments, challenges and emerging applications for current and advanced technologies

01 March 2008 | Edition 37, Wafer Processing
Eric Eisenbraun, College of Nanoscale Science and Engineering (CNSE), The University of Albany, New York, USA Read more >>

Shallow probe metrology

01 March 2008 | Edition 37, Wafer Processing
Addressing the challenges in elemental composition, thickness determination, and dopant dosimetry from FE to BE

Mona P. Moret, Chrystel Hombourger, Francois Desse, Rabah Bengbalagh, Valerie Paret & Michel Schuhmacher, CAMECA, France Read more >>

Front End surface preparation comes of age

01 December 2007 | Edition 36, Wafer Processing
Dave Chapek, Semitool, Montana, USA

X-ray metrology tool for new device materials and structures

01 December 2007 | Edition 36, Wafer Processing
Dr. Paul Ryan, Bede X-Ray Metrology plc, Durham, England Read more >>