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White Papers > Lithography
Lithography efficiency: a cost comparison model
By Sven Grünzig, Nemotek Technologie, Rabat, Morocco
ABSTRACT
The paper presents a calculation model and conclusions with focus on the comparison of low-throughput and high-throughput lithography clusters via an analysis of the lithography Cost of Ownership (COO) and applied data of the Overall Equipment Efficiency (OEE) and Overall Factory Efficiency (OFE). The report will show that the published documents up to today are not sufficient to prove that a higher throughput necessarily leads to an advantage of the manufacturing effectiveness and that it is necessary to calculate and adapt it onto the chip manufacturer’s requirements. It will show metrics and a methodology for fab planners and equipment engineers to calculate the needed cluster throughput and to optimize the lithography efficiency. Furthermore, the calculation model presents a flexible method to identify not only the key drivers to run an efficient production, but also to easily compare different scenarios. Two examples are shown, with models evaluated with real data. This study might also be applicable to other semiconductor processing steps.
Edition 38: The holistic route to high yields at smallest feature sizes
By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole.
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Prospects of incorporating directed self-assembly into semiconductor manufacturing
Developing micro ADI methodology for new litho process monitoring strategies
Defect metrology in water immersion ArF lithography
Tuned Reticle Enhancements Optimized for Process Response
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