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Lithography efficiency: a cost comparison model

By Sven Grünzig, Nemotek Technologie, Rabat, Morocco

The paper presents a calculation model and conclusions with focus on the comparison of low-throughput and high-throughput lithography clusters via an analysis of the lithography Cost of Ownership (COO) and applied data of the Overall Equipment Efficiency (OEE) and Overall Factory Efficiency (OFE). The report will show that the published documents up to today are not sufficient to prove that a higher throughput necessarily leads to an advantage of the manufacturing effectiveness and that it is necessary to calculate and adapt it onto the chip manufacturer’s requirements. It will show metrics and a methodology for fab planners and equipment engineers to calculate the needed cluster throughput and to optimize the lithography efficiency. Furthermore, the calculation model presents a flexible method to identify not only the key drivers to run an efficient production, but also to easily compare different scenarios. Two examples are shown, with models evaluated with real data. This study might also be applicable to other semiconductor processing steps.


Edition 38: The holistic route to high yields at smallest feature sizes

08 January 2009 | Edition 38, Lithography

FT38By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole.


Sources of overlay error in double patterning integration schemes

01 March 2008 | Edition 37, Lithography
David Laidler, Philippe Leray, Koen D’Havé & Shaunee Cheng, IMEC, Leuven, Belgium Read more >>

193nm reticle haze: the dirty little secret and its ultimate solution?

Oleg Kishkovich, Anatoly Grayfer & Frank V. Belanger, Entegris, Inc., Franklin, MA, USA Read more >>

Prospects of incorporating directed self-assembly into semiconductor manufacturing

01 December 2007 | Edition 36, Lithography
R. Singh, T. Boland, R. Mulye, G. Gaur, J.Steelman, D. Arya, N. Srinidhi and P.Deshmukh, Holcombe Department of Electrical and Computer Engineering and Center for Silicon Nanoelectronics, Clemson University, South Carolina, USA Read more >>

Developing micro ADI methodology for new litho process monitoring strategies

01 December 2007 | Edition 36, Lithography
KLA-Tencor and Qimonda

Defect metrology in water immersion ArF lithography

01 September 2007 | Edition 35, Lithography
Uzodinma Okoroanyanwu, AMD, USA; Remo Kirsch & Marcel Grundkowski, AMD Fab 36, Germany; Rene Wirtz & Wolfram Grundke, AMD Saxony LLC, Germany Read more >>

Tuned Reticle Enhancements Optimized for Process Response

01 April 2007 | Edition 33, Lithography
Terrence E. Zavecz, TEA Systems

Overlay control requirements for next-generation lithography

01 April 2007 | Edition 33, Lithography
By Eitan Herzel and Mike Adel, KLA-Tencor Corporation Read more >>

Lithography cell productivity improvement approaches

01 December 2006 | Edition 32, Lithography
Stefan Hempel, Steffen Volt, & Wolfram Grundke, AMD, Dresden, Germany Read more >>