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White Papers > Lithography
Edition 38: The holistic route to high yields at smallest feature sizes
By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole.
Sources of overlay error in double patterning integration schemes
193nm reticle haze: the dirty little secret and its ultimate solution?
Prospects of incorporating directed self-assembly into semiconductor manufacturing
Developing micro ADI methodology for new litho process monitoring strategies
Defect metrology in water immersion ArF lithography
Tuned Reticle Enhancements Optimized for Process Response
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