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White Papers > Edition 26

Can vibration be controlled with damped concrete?

01 June 2005 | Edition 26, Cleanroom
Hal Amick, Ph.D., P.E., Colin Gordon & Associates, San Bruno, CA, USA Read more >>

Automated handling: Unsung hero or enemy of the state?

Mark Osborne, Editor-in-Chief, Semiconductor Fabtech

Making the most of energy conservation

01 June 2005 | Edition 26, EHS
Mark Osborne, Editor-in-Chief, Semiconductor Fabtech

300mm fab automation: Towards 7th heaven

01 June 2005 | Edition 26, Fab Management
Mark Osborne, Editor-in-Chief, Semiconductor Fabtech

In-line purge gas monitoring for 193nm lithography: Detecting acid contaminants at low ppt-levels

01 June 2005 | Edition 26, Lithography
Roel Gronheid, IMEC, Lithography Department, Kapeldreef, Leuven, Belgium, & Rida Al-Horr, Dionex Corporation, Sunnyvale, CA, USA Read more >>

Grand challenges of advanced resist technology

01 June 2005 | Edition 26, Lithography
Jan Makos-Brotherton, Texas Instruments Assignee to SEMATECH, Will Conley, Freescale Semiconductor Assignee to SEMATECH, Kim Dean, SEMATECH, Jeff Meute IBM Assignee to SEMATECH, & Karen Turnquest, AMD Assignee to SEMATECH, Austin, TX, USA Read more >>

Production processes for inducing strain in CMOS channels

Amir Al-Bayati, Lori Washington, Li-Qun Xia, Mihaela Balseanu, Zheng Yuan, Mark Kawaguchi, Faran Nouri & Reza Arghavani, Applied Materials, Inc., USA Read more >>

Channel substrate engineering for the 65nm CMOS technology node and beyond

V. Vartanian, B-Y Nguyen, A. Thean, D. Zhang, S. Zollner, T. White, M. Sadaka, B. Goolsby,
V. Dhandapani, J. Hildreth, L. McCormick, D. Theodore, Q. Xie, X-D Wang, M. Canonico,
M. Kottke, Z. Shi, L. Mathew, M. Zavala, C. Parker, H. Collard, L. Prabhu, R. Rai, S. Murphy,
P. Montgomery, S. Kalpat, M. Ramon, V. Adams, J. Jiang, J. Chen, V. Kaushik, M. Sadd, A. Barr,
A. Vandooren, D. Pham, V. Kolagunta, M. Orlowski, N. Ramani, S. Vanketesan & J. Mogab,
Freescale Semiconductor, Inc., Advanced Products Research and Development Laboratory, Austin, Texas, USA Read more >>

Integration of ALD TaN barriers in porous low-k interconnect for the 45nm node and beyond; solution

W.F.A. Besling & M. Broekaart, Philips Semiconductors Crolles R&D, Crolles, France, V. Arnal, J.F. Guillaumond, A. Farcy & J. Torres, STMicroelectronics, Crolles, France, C. Guedj & L. Arnaud, CEA LETI, Grenoble, France Read more >>

Challenges and trends in copper plating technology for 90nm and beyond

Axel Preusse, AMD Fab 36 LLC & Co. KG & Markus Nopper, AMD Saxony LLC & Co. KG, Dresden, Germany Read more >>