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White Papers > Edition 20

Reliability and packaging verification of Cu/low-k interconnects for

01 December 2003 | Edition 20, Wafer Processing
Wilbur Catabay, Advanced Process Module Development, LSI Logic Corporation, Stan Mihelcic, Advanced Packaging Solutions, LSI Logic Corporation, Jennifer Sabharwal, Deenesh Padhi, Li-Qun Xia & Tony Pan, Applied Materials, Incorporated. Read more >>

Rapid thermal processing of Cu/low-k interconnections for 65-nm technology node and beyond

01 December 2003 | Edition 20, Wafer Processing
R. Singh, A. Venkateshan, & K. F. Poole, Holcombe Department of Electrical and Computer Engineering, Clemson University, Clemson, USA Read more >>

Process optimization – the key to obtain highly reliable Cu interconnects

01 December 2003 | Edition 20, Wafer Processing
A.H. Fischer, A. von Glasow, S. Penka & F. Ungar, Reliability Methodology, Infineon Technologies AG, Munich, Germany Read more >>

Evolution of copper plating chemistry requirements for the sub-90-nm node

01 December 2003 | Edition 20, Wafer Processing
Robert A. Binstead, Jeffrey M. Calvert & Robert Mikkola, Shipley Company, L.L.C., Marlborough, USA Jonathan Reid & John Sukamto, Novellus Systems Inc., Tualatin, USA Read more >>

Confronting the low-k challenge: if it does not improve RC, why bother?

01 December 2003 | Edition 20, Wafer Processing
Drs.Wilbert G. M. van den Hoek, Chief Technical Officer and Executive Vice President of Integration and Advanced Development and CMP Business Group, Novellus Systems Read more >>