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Dr. Paul Ryan, Bede X-Ray Metrology plc, Durham, England
ABSTRACT
Ever since Gordon Moore’s original prediction of how the number of transistors on a chip would increase over time [1], the key method of achieving this increase has been via scaling of the traditional CMOS transistor through improved lithography. By reducing the lateral dimensions, the density of devices can be increased. However, at the 90nm node, issues became evident that suggest that scaling alone would not be sufficient to keep pace with Moore’s law. Physical limits were being reached for the existing materials and it was clear that new materials and processes would have to be integrated into the transistors beyond the 90nm node to keep increasing the density and performance of chips. These new materials include SiGe, high-k/metal gates and porous dielectrics, and new processes - such as process-induced strain - require new metrologies for both development and increasingly to monitor the processes within production.
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