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Ming Yeon Hung, Taiwan Semiconductor Manufacturing Company Xuemei Chen, KLA-Tencor Corporation George Shanthikumar, University of California at Berkeley, CA, USA

ABSTRACT
With shrinking design rules and the transition to 300-mm wafers, the risk and cost associated with process excursions become more severe. With the increased number and value of transistors per wafer, any process or product excursion that goes undetected or is not forestalled, implies significant material at risk and unnecessary production cost. Therefore, a systematic approach to excursion management that ensures effective detection, identification, and reduction of process excursions is essential for realizing the productivity and cost benefits of the technology shifts. In this article, we describe excursion management as applied to overlay in lithography, in the context of a total lithography metrology ROI analysis framework for 300-mm high-volume production.