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Murali Narasimhan, Films and Surface Technology Division, KLA-Tencor Corporation, USA

ABSTRACT

The move from aluminum to copper (Cu) interconnects has been driven primarily by the desire for better device performance. However, the transition to Cu created a number of unexpected challenges that slowed the rate of Cu adoption at the 130- nm node and stalled efforts to integrate low-k dielectrics into the interconnect. With several IC manufacturers now completing the development cycle for their second-generation Cu interconnects for the 90-nm node, process development engineers are now beginning to look at process issues that they are likely to face at 65 nm. What they will find are not incrementally more difficult process integration problems, but rather an entirely new set of challenges that will require the implementation of very specific metrology techniques to keep copper interconnect processing under control. Cu process control issues at the 65-nm node can be broadly classified into five categories: (1) low-k materials; (2) Cu barrier/seed advances; (3) electroplating; (4) Cu chemical mechanical planarization (CMP); and (5) interconnect reliability. This article explores each of these issues in detail and describes the best-known metrology methods currently available to help IC manufacturers bring the copper process under control at the 65-nm node.