L. Broussous, O. Hinsinger, S. Favier, P. Besson, STMicroelectronics, France
ABSTRACT
This work presents an analysis of interconnect cleaning for low-k / copper integration. We focused on post-etch cleaning for 0.12 and 0.09μm node technology with Fluoride Silicon Glass (FSG) and SiOC low-k dielectrics. Electrical and analytical data were combined to point out the mechanisms and efficiency of various cleaning chemistries in the presence of Copper.