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Plasma Doping as an Alternative Route for Ultra-Shallow Junction Integration to Standard CMOS Techno

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DAMIEN LENOBLE, STMicroelectronics, Crolles Cedex, France


The integration of sub-20 nm junctions is scheduled for the sub-90 nm CMOS technologies. The extreme difficulty to implant the doping species at the very low energies required by very-advanced transistor technology (sub-0.1 μm) by standard ion implantation is a strong motivation for device manufacturers to explore alternative doping technology such as PLAD. In this paper, we firstly detail the limits of the ion implantation process and then we show how we have used the PLAD technique to improve the ultra-shallow junction (USJ) process formation.

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