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By Eitan Herzel and Mike Adel, KLA-Tencor Corporation

ABSTRACT

Overlay control has always played an important role in semiconductor fabrication, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind implies short circuits and connection failures, which in turn impact fab yield and profit margins. The importance (and associated difficulty) of controlling overlay has grown exponentially since 90nm, but robustness of overlay measurements has become especially critical as logic and memory IC manufacturers now ramp into high-volume 45nm production, where overlay budgets are shrinking fast (see figure 1) from a relatively relaxed 30% of design rules down to 10% or even less.