Online information source for semiconductor professionals
New CoSi2 Silicidation Process for Sub-0.25 µm MOS Technologies
Popular articles
Voltaix names Peter Smith as CEO - 09 November 2011
Sematech Litho Forum: Sematech mulling multi-beam mask writer effort - 12 May 2010
TSMC hosts 2008 Green Forum on ‘green’ factories - 31 October 2008
Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008
TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008
JAN WAUTERS, KAREN MAEX & ANNE LAUWERS, IMEC, Leuven, Belgium
ABSTRACT
Silicides are used in deep submicron CMOS technologies to lower the sheet resistance of source, drain and gate areas as well as contact and source-drain series resistance. As CMOS p rocesses are scaled down, several problems arise in the silicidation module. There f o re, a trend toward s Co silicidation instead of the widely used Ti silicidation is currently observed across the semiconductor industry. A new Co-silicidation process with a Ti - cap layer shows great promise with scalability towards 0.1 μm.
 |
Please login to download the paper. No account yet? Please register. It's free! |