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New CoSi2 Silicidation Process for Sub-0.25 µm MOS Technologies
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JAN WAUTERS, KAREN MAEX & ANNE LAUWERS, IMEC, Leuven, Belgium
ABSTRACT
Silicides are used in deep submicron CMOS technologies to lower the sheet resistance of source, drain and gate areas as well as contact and source-drain series resistance. As CMOS p rocesses are scaled down, several problems arise in the silicidation module. There f o re, a trend toward s Co silicidation instead of the widely used Ti silicidation is currently observed across the semiconductor industry. A new Co-silicidation process with a Ti - cap layer shows great promise with scalability towards 0.1 μm.
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