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Metal-gate integration challenges

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Kirklen Henson & Malgorzata Jurczak, IMEC, Leuven, Belgium


The introduction of metal gates into CMOS technology faces significant challenges. First, appropriate materials and processes must be identified that give the desired symmetry and magnitude of device threshold voltage. Secondly, a cost-effective integration scheme must be developed for manufacturing. Thirdly, the metal-gate solutions should be scalable to future technologies. Achieving symmetric threshold voltages requires multiple work functions: one for the NMOS and one for the PMOS device. Achieving the desired magnitude of threshold voltage depends on the magnitude of the work function. Planar transistors require a metal-gate solution with work functions near the conduction and valence bands of silicon. Multiplegate transistors and thin-body SOI require work functions near the midgap of silicon and may be compatible with a single midgap material.

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