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Stefan Hempel, Steffen Volt, & Wolfram Grundke, AMD, Dresden, Germany

Abstract

Lithography scanners represent the most cost-intensive tools in a semiconductor facility. Productivity improvements on litho clusters not only increase the whole lithography productivity but also enhance the entire fab performance.

To ensure a cost-efficient lithography process, the scanner should always represent the internal bottleneck within a linked lithography cell. Therefore, it is specifically important to maximize the scanner performance and its output.

This paper provides an overview of methods and approaches to increase the productivity of linked lithography cells. An adaptation model summarizes procedures to adjust track and scanner process times per lithography layer and product. It shows which entity is the actual internal bottleneck and what changes have to be made to achieve a well-working litho cell.

Cell overhead times are investigated and approaches are pointed out to reduce these time losses.

All given facts and methods in this paper are based on a recent successfully accomplished improvement project at AMD Dresden site driven by Industrial Engineering and the lithography department. This team has been very successful in pushing the lithography cell output beyond its earlier projected limits.