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John A. Allgair, Freescale assignee to International SEMATECH Manufacturing Initiative (ISMI), Austin, TX, USA, Benjamin D. Bunday, Mike Bishop & Pete Lipscomb, International SEMATECH Manufacturing Initiative (ISMI), Austin, TX, USA

ABSTRACT

There are numerous metrology challenges facing photolithography for the 45nm technology node and beyond in the areas of critical dimension (CD), overlay and defect metrology. Many of these challenges are identified in the 2005 International Technology Roadmap for Semiconductors (ITRS) [1]. The Lithography and Metrology sections of the ITRS call for measurement of 45/32/22/18nm generation linewidth and overlay. Each subsequent technology generation requires less variation in CD linewidth and overlay control, which results in a continuing need for improved metrology precision. In addition, there is an increasing need to understand individual edge variation and edge placement errors relative to the intended design. This is accelerating the need for new methods of CD and overlay measurement, as well as new target structures. This article will provide a comprehensive overview of the CD and overlay metrology challenges for photolithography, taking into account the areas addressed in the 2005 ITRS for the 45nm technology generation and beyond.