Online information source for semiconductor professionals
Interconnect Strategies and Deep Submicron CMOS Manufacture
Popular articles
Voltaix names Peter Smith as CEO - 09 November 2011
Sematech Litho Forum: Sematech mulling multi-beam mask writer effort - 12 May 2010
TSMC hosts 2008 Green Forum on ‘green’ factories - 31 October 2008
Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008
TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008
KENNETH ROSE & CHRISTOPHER MARK, Rensselaer Polytechnic Institute, Troy, NY, USA
ABSTRACT
As CMOS chips are scaled to deep submicron dimensions, interconnects increasingly limit performance. Achieving performance requirements can lead to an explosion in the number of wiring levels required. Alternative approaches to limiting long wire delay and reducing the number of wiring levels are discussed. Tradeoffs in interconnect strategies are compared.
 |
Please login to download the paper. No account yet? Please register. It's free! |