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Interconnect Strategies and Deep Submicron CMOS Manufacture
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KENNETH ROSE & CHRISTOPHER MARK, Rensselaer Polytechnic Institute, Troy, NY, USA
ABSTRACT
As CMOS chips are scaled to deep submicron dimensions, interconnects increasingly limit performance. Achieving performance requirements can lead to an explosion in the number of wiring levels required. Alternative approaches to limiting long wire delay and reducing the number of wiring levels are discussed. Tradeoffs in interconnect strategies are compared.
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