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W.F.A. Besling & M. Broekaart, Philips Semiconductors Crolles R&D, Crolles, France, V. Arnal, J.F. Guillaumond, A. Farcy & J. Torres, STMicroelectronics, Crolles, France, C. Guedj & L. Arnaud, CEA LETI, Grenoble, France

ABSTRACT

The downscaling of interconnect wiring is facing serious hurdles below 100 nm feature size due to a nonlinear resistivity increase with decreasing linewidth. In order to investigate the increase of copper resistivity for the future technology nodes a novel hard mask spacer patterning technology was used to fabricate very narrow Cu inlaid interconnect trenches in a porous low-k dielectric. ALD TaN and PVD TaN films were deposited on a porous SiOC CVD dielectric material that received a pore-sealing treatment prior to barrier deposition. The parametrical test results showed that in-diffusion of ALD reactants did not take place, resulting in an improved RC performance without degradation of the k-value. The effect of the decreasing linewidth on reliability performance of barrier and porous dielectric was studied by electromigration (EM) and biased thermal stress (BTS) measurements. The extendibility and scalability of atomic layer deposition was shown to be attractive for future process nodes with smaller dimensions.