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VISWESWAREN SIVARAMAKRISHNAN, PRAVIN NARWANKAR, HELEN ARMER, PATRICIA LIU, JUN ZHAO & RAVI RAJAGOPALAN,
Applied Materials, Inc., Santa Clara, CA, USA

ABSTRACT

Gigabit DRAMs will be fabricated with feature sizes <0.13 μm, with cell size equal to 0.14 μm2 and capacitor area equal to 0.051 μm2. These require alternative high k dielectric materials in place of silicon oxide and silicon nitride. The most promising high k dielectric candidate for sub-0.13 μm design rule devices is tantalum pentoxide (Ta2O5). This article discusses issues associated with implementing high k dielectric solutions, including Ta2O5 dielectric deposition, remote plasma oxidation and crystallisation of the Ta2O5, TiN top electrode formation, nitridation of polysilicon, and production worthiness issues of the process.