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Gate spacer engineering for improved boron dose retention

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John Gumpher, Tokyo Electron America, Austin, TX, USA, Narendra Mehta & Wayne Bather, Texas Instruments, Dallas, TX, USA

ABSTRACT

Silicon-based CMOS technologies typically employ SiO2-SiN film stacks as a gate spacer material, primarily due to this film stack’s compatibility with existing process integration. Boron out-diffusion from the source/drain extension regions into the overlying film stack can significantly increase source/drain resistance, resulting in sub-optimal PMOS transistor performance. In addition to thermal budget reduction, material properties of the gate spacer film stack must be tuned to minimize boron diffusion out of the substrate. This study examines the effects of hydrogen incorporation and silicon nitride film stress on boron dose retention; and indicate that increased boron retention can be achieved not only by reduction of hydrogen levels in the silicon nitride film, but also by increasing tensile film stress in the silicon nitride over-layer.

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