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front end surface preparation challenges and solutions for 65- and 45-nm technology nodes

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Jagdish Prasad, AMI Semiconductor, Pocatello, ID 83201, USA

ABSTRACT

There are only minor changes in mateirals and structures at 65 nm and therefore very little change in cleaning strategy for FEOL will be needed. Dedicated single-wafer tools for critical process steps may be needed to avoid cross-contamination. However, dedicated tools to all FEOL processes may be cost prohibitive and therfore it will be necessary to understand the processes that will require dedicated tools. Dilute and batch process will still be the process of choice for DRAM manufacturers but more single-wafer tools may be used by logic device manufacturers.

FEOL wet process will change dramatically at the 45-nm technology node due to introduction of high-k dielectrics and metals for the gate stack. Although metal used for the gate electrodes at 45 nm has not been decided yet, any metal used will possibly dissolve in H2O2 and therefore RCA cleaning as we know it today may no longer be used. Thus all the RCA cleaning advantages such as metal and particle removal are lost at 45 nm and may longer be the FEOL wafer cleaning process of choice at 45 nm.

The loss of Si under the S/D extensions changes the junction profile, thus increasing the S/D resistance and hence the decreasing drive current. Therefore, nonetching processes will be needed to meet this challenge. Dedicated cleaning equipment may be necessary to avoid Hf cross-contamination and thus the use of more single-wafer tools at 45 nm.
 

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