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Andreas Knorr, International SEMATECH/Infineon Technologies, Klaus Pfeifer, International SEMATECH & Bernd Kastenmeier, International SEMATECH/IBM Corporation

ABSTRACT

Relentless device scaling and performance improvements have led to the introduction of low resistance wiring schemes utilizing copper (Cu) interconnects at the 130-nm node technology generation. Equally desirable, but much slower in the development and adaptation proved to be the introduction of low-capacitance interconnect isolation. Degraded thermo-mechanical properties, processing difficulties and increased defectivity were only some of the bumps in the road. With significant delays compared to the roadmap predictions, the currently ramped 90- nm process generation for the first time features wider-spread use of true bulk low- εr materials at εr = < 3.0 resulting in effective wiring permittivity values in the range of 3.0–3.5 depending on the stack geometries, assist layers (etch-stop, CMP hard-mask and dielectric diffusion cap layers) employed [1] and process-induced material modifications. The challenges that need to be overcome will be even more severe for the 65/45-nm technology nodes. Not only are the interconnect geometries anticipated to shrink to < 70 nm in physical size, but the effective permittivity is also expected to be gradually reduced to εr < 2.5.