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Evolution of copper plating chemistry requirements for the sub-90-nm node

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Robert A. Binstead, Jeffrey M. Calvert & Robert Mikkola, Shipley Company, L.L.C., Marlborough, USA Jonathan Reid & John Sukamto, Novellus Systems Inc., Tualatin, USA


The development of the copper damascene process by IBM has revolutionized the design and manufacture of advanced integrated circuits, allowing metal interconnects to shrink with each technology node while maintaining low-resistance wiring pathways. In combination with improvements in the interlayer dielectric materials, the use of copper interconnects has allowed chip designers to reduce the size of active transistor elements, and lower their operating voltage. This has resulted in an overall reduction in RC delay times, so producing smaller, faster devices with lower power requirements. In addition to improved device capabilities, each shrink in technology node has provided the opportunity to lower the cost of manufacture provided that acceptable yield and reliability can be maintained. The copper electroplating process is a key technology that has a significant impact on device yield, and the chemistries used to control the electrodeposition of copper interconnects have had to evolve to meet the stringent requirements of the semiconductor manufacturing processes. In this article we discuss some of the challenges for copper plating chemistries, and illustrate the improvements that have been realized in one of the contending chemistries intended for the sub-90 nm node.

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