Online information source for semiconductor professionals

Electrochemical deposition challenges for 65nm

Popular articles

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

Frank Rabourn, Semitool Inc., Kalispell, Montana, USA

ABSTRACT

The semiconductor industry’s movement to the 65nm technology node, presents a number of challenges for Interconnect. Many of these are extensions of the current challenges for the 90nm node, such as low-k integration, CMP uniformity, Residue Removal and structural robustness. These challenges have become greater when coupled with the 65nm requirements. Newer challenges are directly related to the scaling requirements for 65nm, such as current density, ultrathin barrier/seed deposition and electromigration (EM). This paper is focused on the challenges related to the Electrochemical Deposition (ECD) for the 65nm technology node.

Download Please login to download the paper. No account yet? Please register. It's free!

Related articles

Copper metallization for advanced interconnects: the electrochemical revolution - 01 August 2004

Tool Order: Novellus ships 300th SABRE ECD system - 23 September 2008

Pulsed Electrolytic Deposition of Pt/Au Schottky Contacts on GaAs for Thz Applications - 01 March 2002

Copper Metallization Technology for ULSI Chip Interconnects - 01 March 1999

ASM pushes porous low-k for 65nm - 04 February 2005

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: