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Development of a BEOL post-etch cleaning process for cu/low-k integration using the SEZ single wafer
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L. Broussous, P. Besson, O. Hinsinger, T. Billon, S.A. Henry, M. Frank STM microelectronics, 850;Rue Jean Monnet, F38926, Crolles Cedex, France CEA-Leti, 17 rue des Martyrs, 38054 Grenoble Cedex 09, France SEZ AG, Draubodenweg 29, A9500 Villach, Austria
ABSTRACT
This work represents the investigation of the improvement of cleaning efficiency related to the use of the SEZ Spin Processor 203 in comparison to a static wet bench on Cu on SiOC and porous SiOC structures The focus was on postetch cleaning for 90-nm and 65-nm technology nodes with SiOC and porous SiOC dielectrics. A screening was performed to evaluate chemistries compatible with all the dielectrics involved in SiOC and porous SiOC integration. The chemicals were selected from previous experiments at Leti, in collaboration with Crolles 1 R&D teams, as well as new propositions from chemical suppliers. Electrical and analytical data were used to evaluate the chemicals for post-etch cleaning of Cu and low-k.
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