Online information source for semiconductor professionals
Development of a BEOL post-etch cleaning process for cu/low-k integration using the SEZ single wafer
Popular articles
Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008
Samsung and Micron gain most market share in DRAM crisis - 17 February 2009
TSMC hosts 2008 Green Forum on ‘green’ factories - 31 October 2008
Micron moving fast on Hynix in Q208 NAND flash rankings, says iSuppli - 19 August 2008
Numonyx to close California Technology Center - 12 August 2008
L. Broussous, P. Besson, O. Hinsinger, T. Billon, S.A. Henry, M. Frank STM microelectronics, 850;Rue Jean Monnet, F38926, Crolles Cedex, France CEA-Leti, 17 rue des Martyrs, 38054 Grenoble Cedex 09, France SEZ AG, Draubodenweg 29, A9500 Villach, Austria
ABSTRACT
This work represents the investigation of the improvement of cleaning efficiency related to the use of the SEZ Spin Processor 203 in comparison to a static wet bench on Cu on SiOC and porous SiOC structures The focus was on postetch cleaning for 90-nm and 65-nm technology nodes with SiOC and porous SiOC dielectrics. A screening was performed to evaluate chemistries compatible with all the dielectrics involved in SiOC and porous SiOC integration. The chemicals were selected from previous experiments at Leti, in collaboration with Crolles 1 R&D teams, as well as new propositions from chemical suppliers. Electrical and analytical data were used to evaluate the chemicals for post-etch cleaning of Cu and low-k.
 |
Please login to download the paper. No account yet? Please register. It's free! |