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Design and process limited yield at the 65-nm node and beyond

01 December 2005 | By Mark Osborne | White Papers > Edition 28, Lithography

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Kevin Monahan and Brian Trafas, KLA-Tencor Corporation, Milpitas, California 95035, USA

ABSTRACT

Immersion lithography at 193 nm has emerged as the leading contender for critical patterning through the 32-nm technology node. Super-high NA, along with attendant polarization effects, will require reoptimization of virtually every resolution enhancement technology and the implementation of advanced process control at intrawafer and intrafield levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint DFM and APC strategies at the 65-nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control.
 

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