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Defect Reduction Methodology in the Lithography Module

01 December 1999 | By Mark Osborne | White Papers > Edition 10, Lithography

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INGRID B. PETERSON, KLA-Tencor Corporation, Milpitas, CA, USA

ABSTRACT

One of the challenges facing the implementation of DUV and advanced i-line lithography processes in production is that of maintaining low defect density in order to minimize the impact on yield. Yield depends on the complex interaction between design, CD and overlay control, films, electrical parameters, and defects. As the geometries shrink and the chip size increases, defect reduction becomes increasingly important. Defect density is just as important as critical dimension and overlay metrology in the development and implementation of lithography processes. Achieving and maintaining low-defect density lithography processes necessary for sub-quarter micron technologies requires a defect reduction methodology that quickly detects critical defects, reduces yield-limiting excursions and minimizes cost. This methodology encompasses test and product-wafer inspections combined with a careful selection of the defect inspection tool. Automated defect classification, (ADC) cuts the time to results: it facilitates defect source isolation (essential in defect-level baseline reduction) and excursion control enabling an easy implementation of SPC limits by critical defect types. A sampling strategy that balances the cost due to inspection versus cost due to defect excursions is required.
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