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Uzodinma Okoroanyanwu, AMD, USA; Remo Kirsch & Marcel Grundkowski, AMD Fab 36, Germany; Rene Wirtz & Wolfram Grundke, AMD Saxony LLC, Germany

ABSTRACT

The product pilot lines of the leading-edge IC fabs in the world today are fine tuning their immersion lithography processes for patterning devices at the 45nm technology node, in  preparation for high volume production in 2008. Within a relatively short time,  immersion lithography has made the transition from a mere research curiosity just three years ago to a technology that has shown significant and demonstrable device yield, and is now poised for large scale deployment across the 45nm node device product line. This is a remarkable achievement, which underscores the enormous progress made in the realm of defectivity and overlay control – the twin achilles heels of immersion lithography. While many papers have been published on the sources [1], origins [1] and impacts of these defects [1,2,3], as well as on improvements [3] in exposure tools, tracks, and process chemicals to reduce these defects, there exists a paucity of data on the defect metrology required for inspecting and monitoring immersion lithography defects. This paper is an attempt to remedy the situation. In particular, the thrust of the paper will comprehend the subtleties inherent in the inspection and monitoring of immersion defects relative to those of dry lithography, while at the same time providing a comprehensive overview on the genealogy of such defects, which should make for easy classification and characterization of defects, as well as aid in the debugging of immersion lithography-based process technologies.