Online information source for semiconductor professionals

Comparing Contact and Non-Contact Technology for Post-CMP Cleaning

Popular articles

Micron moving fast on Hynix in Q208 NAND flash rankings, says iSuppli - 19 August 2008

Numonyx to close California Technology Center - 12 August 2008

Qimonda starts major reorganization: exits PC DRAM market - 13 October 2008

Applied Materials sees higher CapEx spending for 2009 - 15 August 2008

Micron close to Inotera share purchase, says Gartner - 06 October 2008

KATRINA MIKHAYLICHENKO & MIKE RAVKIN, Lam Research Corp., Fremont, CA, USA
DAVE STEIN & DALE HETHERINGTON, Sandia National Laboratory, Albuquerque, NM, USA

ABSTRACT

Lam Research and Sandia National Laboratory have conducted studies that compare the cleaning capabilities of non-contact megasonic cleaning with contact cleaning that uses brush scrubbing. We found that partially planarised features are far more difficult to clean than polished blanket dielectric or metal surfaces. Features with larger step heights and/or small horizontal dimensions may efficiently trap slurry and are, of course, difficult to clean. To investigate the effect of topography size and aspect ratio on the relative cleaning efficiency of spin-rinse-dry (SRD), megasonic, and brush scrubbing techniques, special masks with topography of variable size and aspect ratio were developed. Trenches, holes, and corners from 0.6 to 4.0 microns in size with aspect ratio changing from 1:1 to 4:1 were etched in PETEOS film. Two groups of wafers were then used for the tests. Group I wafers were dipped in fumed silica, colloidal silica or Al2O3 slurry and cleaned using either a megasonic cleaning or a brush scrubber. Group II wafers were polished with the same slurries to remove various amounts of material and then cleaned using the same tool sets. In this paper we present the results obtained with different cleaning parameters and chemicals. Our results indicate that it is extremely difficult to remove slurry from deep features after CMP regardless of the cleaning technique. In conclusion, we show that both the step height and the horizontal dimension of the feature are crucial to the cleaning capability of a specific cleaning technique.

Download Please login to download the paper. No account yet? Please register. It's free!

Related jobs

Nanofabrication Facility Operations Manager - National Institute of Standards and Technology - Gaithersburg, 28 August 2008

Embedded Control Systems HW & SW Engineer-Semiconductor Processing Equipment! - MKS Instruments, Inc. - Wilmington, 05 September 2007

Principal Embedded Software Engineer - MKS Instruments, Inc. - Wilmington, 05 September 2007

Staff R&D Engineer - Synopsys - Mountain View, 23 August 2007

Technical Support Engineer - Carl Zeiss SMT, Inc. - Peabody, 10 August 2007

Related articles

Post-CMP Cleaning of Thermal-Oxide Wafers - 01 June 2000

Effective Contact Post-CMP Cleaning - 01 March 1999

CMP chemistry and materials challenges for ultra low-k integration - 01 December 2006

New Product: SEZ’s ‘Esanti’ platform tackles 45nm volume production single wafer FEOL cleaning - 28 November 2006

Evaluation of Brush Post-CMP Cleaning of Thermal Oxide Wafers Using Chelating Basic Chemistry - 01 December 2002

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: