Online information source for semiconductor professionals

CMOS integration results for the 90nm technology node

Popular articles

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

M. Jurczak, E. Augendre & M. Van Bavel, IMEC, Leuven, Belgium & C. Dachs, Philips Research, Leuven, Belgium

ABSTRACT

90nm CMOS process integration requires optimized CMOS process flows and modules with respect to previous technology nodes. This paper presents IMEC’s integration solutions for a few critical process steps, of which the results meet or even exceed the ITRS 2001 specifications. One of the main issues concerns the optimization of the gate dielectric and its reduction to a targeted equivalent oxide thickness below 2.2nm. The effect of a remote-plasma nitridation (RPN) treatment, which introduces high amounts of nitrogen into the oxide, has been studied on gate dielectrics for 90nm low-power CMOS applications, where gate leakage is of major concern. Further, RPN gate dielectrics were optimized for both high-performance and low-power transistors, leading to CMOS performance suitable for portable applications. Secondly, an optimized (conventional) STI module is presented as a lateral isolation technique, preserving gate oxide integrity and providing excellent control of narrow channel effects. Optimization is achieved by minimization of the oxide etching steps. And finally, it will be demonstrated that conventional Co silicide can still be integrated in (sub-)90nm CMOS processes using an elevated silicide architecture, without compromising the transistor performance.

Download Please login to download the paper. No account yet? Please register. It's free!

Related articles

X-ray metrology tool for new device materials and structures - 01 December 2007

Electrochemical deposition challenges for 65nm - 01 March 2003

IMEC shows record 22nm SRAM cell density using EUV - 22 April 2009

Texas Instruments targets 90nm process for 300mm wafers - 04 February 2005

SOI process from Leti capable of 22nm low power devices - 19 October 2009

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: