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CMOS integration results for the 90nm technology node

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M. Jurczak, E. Augendre & M. Van Bavel, IMEC, Leuven, Belgium & C. Dachs, Philips Research, Leuven, Belgium


90nm CMOS process integration requires optimized CMOS process flows and modules with respect to previous technology nodes. This paper presents IMEC’s integration solutions for a few critical process steps, of which the results meet or even exceed the ITRS 2001 specifications. One of the main issues concerns the optimization of the gate dielectric and its reduction to a targeted equivalent oxide thickness below 2.2nm. The effect of a remote-plasma nitridation (RPN) treatment, which introduces high amounts of nitrogen into the oxide, has been studied on gate dielectrics for 90nm low-power CMOS applications, where gate leakage is of major concern. Further, RPN gate dielectrics were optimized for both high-performance and low-power transistors, leading to CMOS performance suitable for portable applications. Secondly, an optimized (conventional) STI module is presented as a lateral isolation technique, preserving gate oxide integrity and providing excellent control of narrow channel effects. Optimization is achieved by minimization of the oxide etching steps. And finally, it will be demonstrated that conventional Co silicide can still be integrated in (sub-)90nm CMOS processes using an elevated silicide architecture, without compromising the transistor performance.

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