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Chip Scale Package Implementation Issues
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ABSTRACT
Availability of board solder joint reliability information is critical to the wider implementation of Chip Scale Packages (CSPs). The JPL-led CSP Consortia, ref. [1], of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of CSPs for a variety of projects. In the process of building the Consortia test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of CSP test vehicles.
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