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MAJEED FOAD, GAËL DE COCK, ADRIAN MURRELL, ERIK COLLART AND DEAN JENNINGS,
Applied Materials, Inc., Santa Clara, CA, USA

ABSTRACT
 
In order to form junctions shallower than 0.1 μm, a size re q u i red for the source/drain extensions for 0.18 μm technology and beyond, boron and arsenic ions have been implanted in crystalline and pre - amorphised Si at 0.5–1 keV and doses of 1x101 4–1 x 1015cm–2 using an Applied Materials xR LEAP ion implanter. Implanted wafers were subsequently annealed in an RTP Centura using ~ 1–20 s soak time and temperatures between 900–1100ºC. Ramp up rates between 75ºC/s and 150ºC/s were examined. Junctions with depths between 25–70 nm (taken at 1x101 8 c m– 3 SIMS B concentration) can be formed routinely with sheet resistance tuneable between 300–900 W/ using Ge pre-amorphisation, and subsequent spike annealing at ramp up rates of 150ºC/s in a nitrogen atmosphere . It was found that sheet resistance (Rs) is most dependent on the spike anneal temperature, while the ramp up rate appears to have a minimal eff e c t on reducing Rs or controlling junction depth (cj). The oxygen content in the RTA ambient is an important parameter in controlling both Rs and cj . The re-crystallisation of pre-amorphised wafers after spike annealing has been evaluated using high resolution transmission electron microscopy (HRTEM). Finally, data from 0.15 μm PMOS transistors have been discussed.