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Prashant Majhi, (Assignment from: Philips Semiconductors), Huang-Chun Wen, Gennadi Bersuker, George Brown, Byoung-Hun Lee, (Assignment from: IBM), & H. Huff, SEMATECH, Austin, Texas, USA

ABSTRACT

The economics of IC manufacturing has driven the decrease of device sizes, while increasing the wafer size to bring down the cost per function for both mixed signal and digital processes. The cornerstone of all logic circuits, the transistor gate stack module, has been successfully scaled for about two decades using conventional materials, SiO2-type gate dielectric and poly-Si gate electrode. However, SiO2-type materials are reaching their physical limits of scaling due to high gate leakage associated with the direct tunneling of the carriers between the electrode and substrate, which is the dominant leakage mechanism in the case of ultrathin dielectrics. The 2003 ITRS suggests that the low-power applications will require a new type of gate dielectric material, the high-permittivity dielectrics (high-k) by the year 2006, while the high-performance devices will soon require both high-k dielectrics and metal-gate electrodes to eliminate poly depletion as devices scale down to the 1-nm equivalent oxide thickness (EOT). In this respect, the metal gates have many very important features, in particular, lower gate resistance, elimination of the B penetration from the doped poly-Si into the gate dielectric and transistor channel, and apparently smaller (compared to poly-Si) interaction of the gate materials and the underlying high-k films. This article summarizes challenges and opportunities that lie ahead in screening candidate metal gate electrodes and their integration in a standard CMOS process in order to replace the aging poly-Si gate electrodes.