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A New Approach for Scheduling Semiconductor Wafer Fabs
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JOHN W. FOWLER, W. MATTHEW CARLYLE, GEORGE C. RUNGER & ESMA S. GEL, Arizona State University, USA
SCOTT J. MASON, University of Arkansas, Fayetteville, AR, USA
OLIVER ROSE, University of Würzburg, Germany
ABSTRACT
According to the 1997 National Technology Roadmap for Semiconductors (NTRS), the cost of equipment is approaching 90% of wafer fab capital costs. The NTRS indicates that in order to utilise this equipment effectively, “significant improvements in factory planning/scheduling” are required. However, scheduling semiconductor-manufacturing facilities is a very difficult problem and is among the most complex scheduling problems encountered today. There are several main features that complicate scheduling these systems, including: a large number of processing steps, re-entrant flows, batch tools, planned and unplanned equipment downtimes, sequence-dependent tool setups, high levels of automation, and the fact that some processing steps require auxiliary resources (e.g. reticles).
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