Online information source for semiconductor professionals
Edition 38: CMOS 32nm technology node: business as usual for interconnect damascene patterning?
Popular articles
New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011
Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008
â??Velocityâ?? the new buzzword in Intelâ??s PQS annual awards - 12 April 2012
Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008
New Product: ASML Brionâ??s Tachyon MB-SRAF enables OPC-like compute times - 19 September 2011
By Gerald Beyer, Ivan Ciofi, Jan Van Olmen, Laureen Carbonel, Steven Demuynck, Janko Versluijs, Vincent Wiaux, Maaike Op de Beeck, Mireille Maenhoudt, Herbert Struyf, Dirk Hendrickx, Jean-Francois de Marneffe, Guy Vereecke, Martine Claes, Twan Bearda, Henny Volders, Nancy Heylen, Youssef Travaly, Michele Stucchi, Zsolt Tokei & Rudi Cartuyvels, IMEC, Leuven, Belgium
ABSTRACT
Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed.
 |
Please login to download the paper. No account yet? Please register. It's free! |