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White Papers

Edition 38: The holistic route to high yields at smallest feature sizes

08 January 2009 | Edition 38, Lithography

FT38By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole.


Edition 38: Metrology equipment for the 45-32nm nodes

11 December 2008 | Edition 38, Wafer Processing
FT38For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Read more >>

Sources of overlay error in double patterning integration schemes

01 March 2008 | Edition 37, Lithography
David Laidler, Philippe Leray, Koen D’Havé & Shaunee Cheng, IMEC, Leuven, Belgium Read more >>

193nm reticle haze: the dirty little secret and its ultimate solution?

Oleg Kishkovich, Anatoly Grayfer & Frank V. Belanger, Entegris, Inc., Franklin, MA, USA Read more >>

Emerging materials in semiconductors

Mark Thirsk & Mike Corbett, Linx Consulting LLC, Massachusetts, USA Read more >>

Special valve configurations and evolutions for new ALD precursors

John Baxter, Swagelok Company, Solon, OH, USA

The effect of HCl permeaton through PFA on expected component life

Don Grant & Debra Carrieri, CT Associated, Inc., Eden Prairie, Minnesota, USA Read more >>

Advanced process control of copper electroplating thickness profile

Sai Boyapati, Kevin Chamness, Frank Smith, Patrick Cowan & John Crowley, Spansion, Inc., Austin, Texas, USA Read more >>

Meeting the doping challenges: the case for plasma doping

01 March 2008 | Edition 37, Wafer Processing
Jose I. Del Agua, Tze Poon, Pete Porshnev $ Majeed Foad, Applied Materials, Inc., Santa Clara, California; Malgorzata Jurczak, Jean-Luc Everaert & Wilfrid Vandervorst, IMEC, Leuven, Belgium Read more >>

Contamination control for the 32nm node

01 March 2008 | Edition 37, Wafer Processing
Twan Bearda, Rita Vos, Paul W. Mertens, Gabriela Catana & Cedric Huyghebaert, IMEC, Leuven, Belgium Read more >>