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By Sven Grünzig, Nemotek Technologie, Rabat, Morocco

ABSTRACT
The paper presents a calculation model and conclusions with focus on the comparison of low-throughput and high-throughput lithography clusters via an analysis of the lithography Cost of Ownership (COO) and applied data of the Overall Equipment Efficiency (OEE) and Overall Factory Efficiency (OFE). The report will show that the published documents up to today are not sufficient to prove that a higher throughput necessarily leads to an advantage of the manufacturing effectiveness and that it is necessary to calculate and adapt it onto the chip manufacturer’s requirements. It will show metrics and a methodology for fab planners and equipment engineers to calculate the needed cluster throughput and to optimize the lithography efficiency. Furthermore, the calculation model presents a flexible method to identify not only the key drivers to run an efficient production, but also to easily compare different scenarios. Two examples are shown, with models evaluated with real data. This study might also be applicable to other semiconductor processing steps.

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By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper.

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By Mark R. Litchy, CT Associates, Inc., Minnesota, USA & Reto Schoeb, Levitronix, LLC, Massachusetts, USA. - ABSTRACT - The production of semiconductor devices continues to be extremely sensitive to particulate and metallic contamination. As feature sizes continue to decrease, the need for purity will continue to increase. Various types of pumps are used in bulk chemical delivery systems, recirculating etch baths, and other high purity process applications. Many of these pumps shed significant quantities of particles that may reduce product yield or impact the performance or lifetime of filters used in the process loop. Furthermore, metallic contamination in process chemicals can cause a variety of yield-related issues. This paper evaluates the levels of trace metal extraction and particle shedding under different operating conditions using two high purity pump types from three manufacturers. Read more >>

Worsening global economic conditions in the second half of 2008 has started to seriously impact the semiconductor industry. Weakening demand in all major device sectors is causing fab utilization to fall, while more 300mm fab expansions and new fab construction has been put on hold. The six-month review covered in this report highlights the rapidly changing dynamics with regard to fabs on hold and expected tool install schedules, and provides a review of the foundry sector. Read more >>

By Ernst Richter et al - ABSTRACT - This article follows up on a previously published paper that introduced the 110nm technology transfer of Dynamic Random Access Memory (DRAM) for the Inotera Memories joint venture at start-up [1]. In this paper, technology transfer and ramp of the 75nm DRAM technology is outlined for Inotera in full production mode. Again, technology transfer was done from Qimonda (previously Infineon Technologies) at Dresden in Germany where the technology was jointly developed with Nanya Technologies. Inotera at Taoyuan in Taiwan was the first receiving site to repeat the technology qualification. Continuous sales price reduction puts pressure on memory firms for fast introduction of technology shrinks to remain cost competitive [2]. Delays as short as a few days in the production ramp can translate into millions of dollars of missed opportunity in revenue. This paper sets forth the steps taken by the two companies to avoid such setbacks in the technology transfer. Read more >>

By Chuck Extrand, Entegris, Chaska, Minnesota, USA - ABSTRACT - Polymers, commonly referred to as plastics, are widely used in the manufacturing of microelectronic devices. In addition to their many desirable properties, such as low cost, light weight, strength, ductility and ease of processing, polymers can be created free of metals and inorganic constituents that may interfere with sensitive clean room fabrication processes in multiple ways. For example, the loose molecular structure of polymers may allow the unwanted permeation of gases and simple liquids in fabrication facilities. This paper will provide a brief introduction to factors that influence permeation through polymers, discussing polymer structure background and its relation to permeation, and the influences of various polymer properties on permeation. Read more >>

By David Jimenez & Daren Dance, Wright Williams & Kelly, Inc., Pleasanton, California, U.S. - ABSTRACT - In April of 2007, WWK conducted a survey of semiconductor industry professionals and asked several questions pertinent to the semiconductor manufacturing industry, including the respondents’ expected arrival date of 450mm wafers and the likelihood of direct write patterning being incorporated into more manufacturing processes. A follow-up survey was carried out in 2008, and these combined sets of data are portrayed in a projection of a typical manufacturing facility in 2013. Read more >>

By Brandon Lee & Susanta Dash, CIMAC, San Jose, California, U.S. - ABSTRACT - Performance testing is carried out on an MES system to identify and eliminate bottlenecks that can potentially cause production outages and lost revenue in a semiconductor production fab. In a distributed system, bottlenecks can occur at the client site, within the server or in the  network. The MES system is the heart of the manufacturing operation and interacts with a number of other systems to support the manufacturing line in a fab. As production increases with ramping up of the production volume, the loads on the various systems that support the production also increase. This paper puts forward the potential benefits in applying the MES system for testing and validation of performance and scalability to measure the various key parameters, thus providing good ROI by early detection of potential problems. Read more >>

By Terrence Morris & Steve Blaine PE, CH2M HILL, Oregon, USA

Outside of the process tools themselves, the chilled water plant is typically the single largest consumer of electrical energy in a semiconductor facility. This load includes not just chillers but also cooling tower fans, primary pumps, secondary pumps and condenser pumps. In order to meet the cooling requirements for any particular heat load, many different combinations of this equipment can be run. However, electricity consumption varies considerably depending on the combination of equipment used and the operating levels of the individual components. Selecting the optimal mix of equipment and operating levels presents a substantial challenge for an automatic control system and plant operators. Typically, no method is available to predict the effect of interactions and variations in load demand and outside air. This makes it challenging, if not impossible, to find an equipment mix that achieves optimal energy use. In response to this challenge, we set out to create a model/tool that would allow operators to automatically determine the optimal equipment mix to satisfy cooling requirements and minimize energy use. This paper describes how this model was created and how it works.

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By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Read more >>