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A leading foundry in Taiwan has selected Camtek's Falcon Automatic Optical Inspection (AOI) system, for metrology and inspection solutions for the 3D IC processes. The Falcon 830plus system was evaluated and selected over its competitors after demonstrating the best-of-breed performance in this challenging arena, according to the company. Read more >>

IMEC is to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs) as part of the nano-electronics research centre’s to accelerate development efforts.
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Citing strong demand across virtually all its market segments, which include semiconductor, LCD display and crystalline silicon solar, but not thin-film solar, Applied Materials expects FY2010 sales to be over 50% greater than the previous year. Applied had previously guided sales would increase by approximately 30%.
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By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper.

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By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Read more >>

For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Read more >>