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Wafer Processing

News

Infineon sells Wireless Solutions Business to Intel for US$1.4 billion cash

31 August 2010
Peter 
Bauer of Infineon TechnologiesIntel has strengthened its position in the wireless technology stakes by purchasing Infineon’s Wireless Solutions (WLS) business. The cash transaction, valued at approximately US$1.4 billion, will see the WLS segment operate as a standalone business for its existing customers, while also contributing to Intel’s aim of further developing its connected computing capabilities. Read more >>

Toshiba starts mass production of 24nm process NAND flash

31 August 2010
ToshibaLaunching what has become known as the world’s highest capacity single-chip 64Gb memory, Toshiba has announced that it has begun volume production of NAND flash memories fabricated with 24nm process technology. Use of this 24nm technology will drive the further shrinkage of chip sizes, allowing the highest density on a single chip. Read more >>

Samsung eyes top spot in IC fabrication as revenues rival Intel’s

27 August 2010
Samsung DRAMAfter over 20 years of stasis in the pecking order of IC manufacturing revenues, it looks like Samsung’s remarkable rise in performance of late might see the company overtake current leader Intel as soon as 2014. A combination of data from IC Insights’ Strategic Reviews Online database of worldwide semiconductor companies and the McClean Report 2010 Mid-Year Update’s five-year market forecasts suggest that Samsung’s current revenue growth, if maintained at its current rate, will overtake that of Intel, replacing the long-serving industry leader. Read more >>

Product Briefings

New Product: UVision 4 defect inspection system from Applied handles patterning layers at 22nm

17 June 2010
UVision 4 system from Applied MaterialsProduct Briefing Outline: Applied Materials has launched the ‘Applied UVision’ 4 wafer inspection system, enabling IC manufacturers to detect yield-limiting defects in the critical patterning layers of 22nm and below logic and memory devices. UVision 4 extends Applied’s DUV laser imaging technology to deliver the sensitivity and productivity needed to rapidly locate and identify defects previously unseen by any other inspection system. The UVision 4 system is already the tool of record at multiple leading flash manufacturers where it is used for 32nm production and in the development of 22nm and EUV lithography processes. Read more >>

New Product: Applied Materials’ InVia system tackles HAR liner film deposition for TSV structures

15 April 2010
‘Applied Producer InVia’ dielectric deposition system. Product Briefing Outline: Applied Materials has added to its line of 3D chip packaging solutions with the launch of its ‘Applied Producer InVia’ dielectric deposition system. Using a unique CVD process and chemistry, the InVia system deposits the critical oxide liner film layer in high aspect ratio (HAR) through-silicon via (TSV) structures. Providing conformal coverage over the full depth of these challenging features, the InVia process enables robust electrical isolation of the TSV – which is vital for reliable device performance.  Read more >>

New Product: ASM’s new PowerFill epitaxial technology enables void free filling of deep trenches

21 January 2010
Product Briefing Outline: ASM International has developed its ‘PowerFill’ epitaxial silicon (Epi Si) trench fill process, which enables void free filling of deep trenches with doped, epitaxial silicon. PowerFill is claimed to be about 3 times faster than competing processes, reducing manufacturing costs and creating an additional degree of freedom in power device design. Fairchild Semiconductor is the first customer to qualify the process for its advanced power management devices, having completed verification at its fab in Korea. ASM believes the new process enables power management devices and circuits to be realized in a smaller footprint thereby reducing die cost and form factor. Read more >>

White Papers

PREVIEW: Edition 39: Wafer-edge yield engineering in leading-edge DRAM manufacturing

12 March 2009

FT 39By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper.

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Edition 38: CMOS 32nm technology node: business as usual for interconnect damascene patterning?

15 January 2009
FT38By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Read more >>

Edition 38: Metrology equipment for the 45-32nm nodes

11 December 2008
FT38For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Read more >>