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SUSS MicroTec, supplier of process and test solutions for microstructuring applications in semiconductor markets, is changing the structure of its sales in Asia and basing the new office in Singapore. ZMC Technologies will act as general sales representative for interests in Malaysia, Singapore and the Philippines. This adds to SUSS MicroTec’s presence in Seoul, Shanghai, Yokohama, and Hsinchu. Read more >>

The list of metrology equipment supplier acquisitions at Semilab continues to lengthen with the announcement that it has purchased privately held Semiconductor Diagnostics, Inc. (SDI) for an undisclosed sum. SDI, based in Tampa, Florida is known for its range of non-contact measurement solutions was founded in 1988 and has 380 systems installed in fabs worldwide. SDI had also started offering services to the PV industry. Read more >>

With the help of its process partner IBM, SMIC has said it has produced device yields from test lots for its germanium strained high-performance 45nm process offering. SMIC has previously qualified IBM’s 45nm bulk CMOS low-power process. Read more >>

By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper.

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By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Read more >>

For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Read more >>