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Wafer Processing


Centrotherm subsidiary joins Sematech‚??s FEP to research low-temperature processing techniques

10 April 2012

The latest machines are installed at Cnetrotherm's base last yearSematech has announced that the centrotherm photovoltaics AG subsidiary, centrotherm thermal solutions, will join its Front End Program (FEP) to develop low-temperature processing techniques for use in high-performance logic and advanced memory applications such as metal oxide RRAM devices.



Tool Order: Himax Technologies places repeat order for EV Group‚??s IQ Aligner system

28 March 2012

Himax Technologies, a leading producer of CMOS image sensors, semiconductor devices and power management devices, has placed a repeat order for an IQ Aligner UV nanoimprint lithography (UV-NIL) system from EV Group. The IQ Aligner system will be shipped and installed at Himax’s Tainan facility in Taiwan.



Tool Order: Camtek tapped for US$3.5 million worth of Falcon wafer inspection tools

27 March 2012

A Camtek Falcon 2D and 3D inspection modelCamtek, the automated and technological solution provider, has announced that it has booked orders exceeding US$3.5 million for its Falcon family of automated wafer inspection products. The order was from an unnamed global outsourced semiconductor assembly and test house (OSAT) and pertains to various applications within the backend semiconductor process. The product delivery will come in the current and following two quarters.


Product Briefings

Novellus’ conformal film deposition suite offers 100% step coverage

12 July 2011
Product Briefing Outline: Novellus Systems has launched the ‘VECTOR CFD’ family of films for the company’s VECTOR Express, VECTOR Extreme and VECTOR Excel plasma-enhanced chemical vapor deposition (PECVD) systems.  The Conformal Film Deposition (CFD) suite of dielectric films consists of oxide, doped oxide and nitride films are deposited at temperatures ranging from 50 degrees to 450 degrees Celsius.  These films provide solutions for emerging sub-2X nm logic and memory applications, including front-end-of-line (FEOL) liners and spacers used in tri-gate transistors and FinFETs, bitline spacers, and through silicon via (TSV) dielectric liners, amongst other applications. Read more >>

Applied Materials launches three new products for improving DRAM transistor performance

06 July 2011
Product Briefing Outline: Applied Materials has launched a trio of new systems designed to boost performance in the next generations of DRAM chips. These systems are claimed to overcome key challenges in fabricating the transistor and contact areas of memory chips, include: the ‘Applied Centura DPN HD’ system to improve the gate insulator scaling; the ‘Applied Endura HAR Cobalt PVD’ system for high aspect ratio contact structures; and the ‘Applied Endura Versa XLR W PVD’ system for reduced gate stack resistance. Read more >>

New Product: Applied Materials Applied ‚??Vantage Vulcan‚?? RTP system overcomes wafer ‚??hot spots‚

29 June 2011
Applied Materials ‘Vantage Vulcan’ RTP systemProduct Briefing Outline: Applied Materials has introduced the Applied ‘Vantage Vulcan’ rapid thermal processing (RTP) system. The system is claimed to supersede current RTP technology to bring a new level of precision and control to the anneal process, enabling chipmakers to reduce variability and boost production yields of their most highly-valued, highest-performing devices. Read more >>

White Papers

PREVIEW: Edition 39: Wafer-edge yield engineering in leading-edge DRAM manufacturing

12 March 2009

FT 39By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper.


Edition 38: CMOS 32nm technology node: business as usual for interconnect damascene patterning?

15 January 2009
FT38By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Read more >>

Edition 38: Metrology equipment for the 45-32nm nodes

11 December 2008
FT38For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Read more >>