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Product Briefings > Wafer Processing

New Product: Alchimer launches cost-saving ‘AquiVia’ deposition process

09 July 2009 | Wafer Processing
Product Briefing Outline: Alchimer S.A has launched its cost-saving ‘AquiVia’ deposition process. The AquiVia process is claimed to reduce overall cost of ownership for through-silicon via (TSV) metallization by up to 65% vs. conventional dry processes. Alchimer’s new process encompasses three distinct process steps required before the TSV can be filled with metal. It enables wet-process deposition of insulator, barrier and copper seed layers within high-aspect ratio TSVs, using Electrografting technology. Read more >>

New Product: Nova’s ‘MatMaker,’ solution significantly cuts optical CD measurement time

02 July 2009 | Wafer Processing
Product Briefing Outline: Nova Measuring Instruments has launched ‘MatMaker,’ a Product-Driven Materials Characterization package, which is based on software algorithms and tools refined by Nova’s applications developers over the past 10 years. The company claims the new software changes the way spectral Optical CD is deployed in fabs, significantly reducing application development time and cost while at the same time increasing the measurement accuracy. Read more >>

New Product: Peter Wolters double-sided silicon wafer polishing handles 22nm node

25 June 2009 | Wafer Processing
Product Briefing Outline: Peter Wolters GmbH, a wholly-owned subsidiary of Novellus Systems has developed an advanced polishing technology for its MicroLine AC 1500-P³ and AC 2000-P³ double-sided silicon wafer polishing (DSP) systems that will meet the lithography requirements for semiconductor device manufacturing at 22nm and beyond. Read more >>

New Product: Applied Materials upgrades Endura CuBS PVD system for 32-22nm deposition

02 June 2009 | Wafer Processing
Applied ‘Endura CuBS RFX’ PVD systemProduct Briefing Outline: Applied Materials, has launched its Applied ‘Endura CuBS RFX’ PVD system, designed for copper barrier/seed deposition and qualified for 32 and 22nm production by logic and flash memory manufacturers. The system sequentially deposits the Ta(N)/Ta barrier followed by the Cu seed layer under high-vacuum conditions. Integration of the complete sequence, including the Applied’s Aktiv Preclean [chamber or process], on the Endura platform is said to improve film adhesion and oxide-free interfaces, while preserving k-value integrity for low via resistance and high device reliability. Read more >>

New Product: Rudolph’s MetaPULSE-G offers 22nm copper metrology capability

11 May 2009 | Wafer Processing
Product Briefing Outline: Rudolph Technologies is launching its ‘MetaPULSE’-G thin-film measurement tool optimized specifically for copper damascene processes at 45nm through 22nm technology nodes and copper via fill in new 3D IC applications. Read more >>

New Product: 32nm dielectric films from Novellus reduces UV transmission

07 May 2009 | Wafer Processing
Product Briefing Outline: Novellus has developed a suite of 32nm dielectric films which are claimed to significantly reduce the transmission of UV radiation to the critical copper-dielectric interface, maintaining a compressive stress in this region and hence device reliability. Read more >>

New Product: EtchTemp SensorWafer from KLA-Tencor can characterize high-power, high-frequency etch

23 April 2009 | Wafer Processing
Product Briefing Outline: KLA-Tencor has introduced the next-generation in-situ plasma etch wafer temperature measurement product, the ‘EtchTemp SensorWafer.’ The newest SensorWafer from KLA-Tencor’s SensArray division captures the effect of the process environment on production wafers and offers new capabilities to robustly characterize the high-power, high-frequency etch recipes proliferating at 65nm nodes and below. The EtchTemp SensorWafer enables etch engineers to further visualize, diagnose, and control their processes and process tools, through the significantly increased process measurement capabilities. Read more >>

New Product: Novellus’ Suppression-Enhanced Fill technology enables void-free fill of Cu

23 April 2009 | Wafer Processing
Product Briefing Outline: Novellus has developed an innovative copper electrochemical process called ‘Suppression-Enhanced Fill’ (SEF) that eliminates defects when scaling to the 32nm technology node. The SEF process utilizes the capabilities of the company's ‘SABRE Extreme’ platform to simultaneously enhance current suppression on the wafer field and within the upper sidewalls of contacts and trenches while permitting copper deposition to initiate rapidly from the bottom of these features. Read more >>

New Product: Synopsys’s Yield Explorer identifies and eliminates systematic yield limiters

24 March 2009 | Wafer Processing
A built-in layout viewer makes it easy to correlate any yield relevant information to physical designProduct Briefing Outline: Synopsys has introduced Yield Explorer, a new yield management product that expedites the discovery and mitigation of yield limiters in leading-edge integrated circuits. When compared with traditional methods, Yield Explorer can accelerate the first-silicon debug time by an order of magnitude. Read more >>

New Product: Rudolph Technologies offers ‘WaferWoRx’ probing analysis on ‘NSX’ platform

12 February 2009 | Wafer Processing
Product Briefing Outline: Rudolph Technologies has updated its ‘NSX’ Series wafer inspection system, which now includes ‘WaferWoRx’ probing process analysis. The NSX Series can now identify the root cause of probe test failure mechanisms, providing faster problem resolution and improved yield performance. WaferWoRx technology came from the acquisition of Applied Precision’s Semiconductor Division in 2007. Read more >>