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Product Briefings > Wafer Processing

New Product: ‘Applied’s millisecond laser anneal system tackles sensitive NiSi transistor layers

17 December 2009 | Wafer Processing
Product Briefing Outline: Applied Materials has introduced its new ‘Applied Vantage Astra’ millisecond anneal system used for transistor fabrication that enables faster, lower power consumption devices. Targeted for creating the sensitive nickel silicide (NiSi) transistor contact layers in 45nm and beyond logic chips the laser-based system can enhance drive current, and reduce gate leakage by an order of magnitude, helping to significantly increase device performance and yield. According to Applied, the compact design delivers more than twice the wafer output of competing systems and the lowest available cost of ownership (CoO). Read more >>

New Product: Dual polishing action enables Applied’s Reflexion GT CMP system higher productivity

08 December 2009 | Wafer Processing
Product Briefing Outline: Applied Materials has launched the ‘Reflexion GT’ system for advanced metal CMP applications.  The system’s novel dual wafer design is claimed to set new benchmarks in CMP performance and productivity, delivering superior profile control and 60% higher throughput than competing systems. The Reflexion GT also dramatically cuts consumables cost, requiring up to 30% less slurry and processing twice as many wafers per polishing pad. Read more >>

New Product: Ashable hardmask films from Novellus offer 25% greater etch selectivity

26 November 2009 | Wafer Processing
Product Briefing Outline: Novellus Systems has developed a new suite of ashable hardmask (AHM) films that are claimed to have up to 25% greater etch selectivity compared to similar amorphous carbon films in use by the industry today. According to Novellus the highly selective and transparent (HST) AHM family of films has demonstrated die yield improvements as much as 7% when coupled with Novellus’ patented integrated edge bevel removal (EBR) technology. Read more >>

New Product: Automated mechanical monitoring system from InnerSense prevents wafer handling issues

22 October 2009 | Wafer Processing
Product Briefing Outline: InnerSense LTD (a Ricor company) now offers a new wafer handling analysis product, the SMW2, for automated mechanical monitoring of the 300mm semiconductor process tools. The new product offering is based on over 6 years of experience in preventing excursions related to wafers’ micro-cracks and other mechanical defects, as well as providing capabilities to detect worn-out process tool mechanical components and to plan more effective periodic maintenance. Read more >>

New Product: SABRE Excel from Novellus designed to improve plating performance on thin seeds

22 October 2009 | Wafer Processing
Product Briefing Outline: Novellus Systems has launched the SABRE Excel, an advanced copper electroplating system designed to provide fill and defect density performance for the 22nm node and beyond. The platform features a new deposition module incorporating Novellus’ patented IRISCell technology, as well as new hardware, software and communications upgrades to the process tool’s mainframe. Additionally, an advanced plating process has been developed for SABRE Excel to take advantage of these new features. Read more >>

New Product: KLA-Tencor 8900 inspection system designed for CMOS image sensor applications

15 October 2009 | Wafer Processing
8900 defect inspection systemProduct Briefing Outline: KLA-Tencor has extended its product offerings in the CMOS image sensor (CIS) market by announcing the 8900 defect inspection system. The system offers selectable illumination wavelengths, color-matched to CIS pixels; simultaneous brightfield and darkfield optical channels to enable capture of a wide variety of defect types; and adjustable sensitivity and throughput settings for cost-effective defect management from initial product development through volume production of color filter arrays (CFA). An 8900 defect inspection system was recently installed at the first 300mm advanced CFA fab of Toppan Printing. Read more >>

New Product: UV thermal processing treatment from Novellus enables improve low-k hardness

01 October 2009 | Wafer Processing
Product Briefing Outline: Novellus Systems has developed a multiple wavelength UV Thermal Processing (UVTP) treatment on the company’s ‘SOLA’ platform that results in a claimed 25% improvement in film hardness compared to a single wavelength treatment of the same k-value dielectric. It also enables the independent optimization of key UV treatment steps to enhance film performance while maintaining a high level of manufacturability. Read more >>

New Product: Mattson’s Helios XP has low temp RTP capability enabling advanced silicide formation

01 October 2009 | Wafer Processing
Product Briefing Outline: Mattson Technology has launched the Helios XP system, its third generation of 300mm RTP tools. The company noted that its Helios XP system has been in qualification at a major IC manufacturer and it recently shipped a system to a leading foundry customer for advanced anneal processing.  Read more >>

New Product: ‘IONX’ PVD copper seed process from Novellus provides bottom-up fill for 2xnm node

30 July 2009 | Wafer Processing
Product Briefing Outline: Novellus Systems has developed an advanced Hollow Cathode Magnetron (HCM) ‘IONX’ PVD copper seed process that will enable copper interconnects below the 2xnm technology node. The breakthrough will allow the company’s highly-productive and proven HCM PVD technology on the ‘INOVA’ platform to continue to be used for barrier and seed thin film deposition, avoiding the migration to less-productive and costly ALD or CVD approaches. Read more >>

New Product: TSMC’s iDRC and iLVS data formats support 40nm process IC designs

21 July 2009 | Wafer Processing
Product Briefing Outline: Taiwan Semiconductor Manufacturing Company has unveiled interoperable design rule check (iDRC) and layout-versus-schematic (iLVS), two unified electronic design automation (EDA) data formats, for its 40nm process technology. TSMC claims to be the first foundry to collaborate with multiple EDA vendors to create and qualify an interoperable physical verification format that optimizes data delivery and interpretation between physical verification and analysis tools and advanced process technologies. Read more >>