Online information source for semiconductor professionals

Product Briefing Outline: ASML has launched its newest TWINSCANTM XT:1950i lithography system using a 1.35 NA lens, which is claimed to increase the performance of its immersion lithography systems by 25 percent. The system offers improved overlay, resolution and throughput, to enable high-volume manufacturing of more powerful 38nm memory and 32nm logic semiconductors. Read more >>

Product Briefing Outline: ASML and its subsidiary Brion Technologies have introduced the ‘LithoTuner’, a new suite of products that integrates computational and wafer lithography to improve semiconductor manufacturability. LithoTuner Pattern Matcher and LithoTuner Pattern Matcher FullChip are designed to enable scanner matching improvements of between 30-70% over current scanner matching techniques. Pattern Matcher has been made available for ‘TWINSCAN’ ArF immersion, ArF dry and KrF DUV lithography systems. Read more >>

Product Briefing Outline: Applied Materials has launched the ‘Applied Aera2’ for critical dimension uniformity (CDU) lithography applications. Using the system’s ‘IntenCD’ technology in the fab, semiconductor manufacturers can improve CDU by more than 20%, increasing device yield and lowering the per-wafer cost of patterning, according to the company. The Aera2 can be used to extend photomask lifetime and bring productivity gains to the entire lithography cell. Read more >>

Product Briefing Outline: SoftJin, a provider of Customized Automation software for Electronic Design and Manufacturing, has launched NxDAT, software for efficient Analysis of Defects identified by Mask Inspection Systems.  The software supports correlation of defect data with Layout/Mask data in GDSII, OASIS, OASIS.VSB and MEBES format. Other Mask data formats are intended to be supported shortly. Read more >>

Product Briefing Outline: KLA-Tencor is now offering the latest version of its industry-leading computational lithography tool, ‘PROLITH 11.’ The new tool enables users for the first time to evaluate current double-patterning schemes and cost-effectively explore alternate solutions to lithography challenges in design, materials and process development. This new computational lithography tool also supports single-pass patterning and immersion technologies, according to KLA-Tencor. Read more >>

Product Briefing Outline: Dow Corning Electronics' Silicon Lithography Solutions group has now made available its XR-1541 E-Beam Resists, designed to enable the development of next-generation, direct-write lithography processing technology. This family of new advanced spin-on resists, which allow patterning with electron beams, is claimed to enable 6nm features. Read more >>

Product Briefing Outline: Synopsys and Hitachi High-Technologies have developed a seamless link between Hitachi High-Tech's DesignGauge design data measuring system and Synopsys' Proteus optical proximity correction (OPC) solution. Focused on incorporating manufacturing-aware metrology data into design, this common design for manufacturing (DFM) interface assists in the development of faster, more accurate and predictive OPC models for advanced 45nm and beyond technologies. Higher OPC model predictability and reduced model-building cycle times are also achievable. This new functionality is available in the latest production release of Proteus. Read more >>

Product Briefing Outline: TSMC has introduced a new Unified Design For Manufacturing (UDFM) architecture that targets 32nm process technology and smaller geometries and improves yields, lowers design costs and accelerates time-to-market and time-to-volume. The UDFM is intended to provide a unified, encapsulated access to TSMC foundry data and was developed in collaboration with EDA vendors and other design infrastructure partners. The TSMC UDFM is also one of the key collaborative components of the company's recently unveiled Open Innovation Platform. Open Innovation Platform is a platform for innovations, hosted by TSMC and open to TSMC customers and partners. It is built on TSMC's design-enabling building blocks and an ecosystem interface. Read more >>

Product Briefing Outline: Takumi Technology Corporation today announced the availability of its new layout optimization tool - the Takumi Enhance-RO - for automated enforcement of recommended rules and critical area optimization. With Takumi Enhance-RO, Takumi's layout optimization suite now offers complete solutions to address issues that affect parametric yield as well as eliminating catastrophic defects. Read more >>

Product Briefing Outline: Xyalis has launched its GTmask suite, which, it is claimed, is a fully integrated mask date prep solution dedicated to complex wafer masks. Based on Xyalis’ existing tools, GTmask offers new capabilities fully meeting mask teams’ demands, covering wafer assembly and floor-planning for chip arrays, multi-project wafers and multi-layer reticles; CMP metal filling; automatic frame generation; and optimized GDSII and jobdeck files generation. The GTmask tool suite is part of Xyalis’ product strategy aiming at establishing direct links between process data management tools and SQL-based administration databases. Read more >>