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New Product: Ultra-thin SOI and ultra-thin BOX wafers from Soitec support sub-45 nm roadmap

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Product Briefing Outline: Soitec has introduced a new generation of advanced substrates that support all the applications and architectures on the industry’s sub-45 nm roadmap. New solutions such as ultra-thin top silicon and ultra-thin Buried OXide (BOX) give device architects and designers complete flexibility in their choice of substrates for partially depleted (PD) and fully-depleted (FD) devices, including multi-gate transistor architectures (FinFET, Trigate).

Problem: Device architects can leverage substrate design in their solutions for scaling, low power, and greatly reduced threshold voltage variability, thus ensuring SRAM scalability, and in particular stability at low operation voltages and significantly improved soft error rate. This is a major advantage for IC design today. In addition, CMOS process simplifications, and advanced SOI memory solutions—like single transistor body cell or ZRAM— result in a lower cost-of-ownership for SOI ICs

Solution: This new generation of substrates fabricated using the company’s patented ‘Smart Cut’ process is designed to meet the most advanced requirements in terms of defectivity, flatness and SOI thickness control of up to ±10 Angstroms (Å). The top silicon layer of these wafers is available in thicknesses ranging from just 20 nm up to 110 nm, while the BOX can be as thin as 10 nm. Options are also available like High Resistivity substrate and strained SOI.

Applications: Ultra-thin SOI and ultra-thin BOX wafers for sub-45nm.

Platform: The new generation of substrates is built on the highly successful 300mm ‘Unibond’ XUT+ wafers, which are currently shipping to leading customers for the PD 45-nm logic market, and which are also under qualification or sampling with other customers in a variety of system-on-chip applications.

Availability: Currently available.

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This piece of news seems to be 6 months old... Source :
By MaeGeri1 on 30 January 2009

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