Product Briefing Outline: Taiwan Semiconductor Manufacturing Company has unveiled interoperable design rule check (iDRC) and layout-versus-schematic (iLVS), two unified electronic design automation (EDA) data formats, for its 40nm process technology. TSMC claims to be the first foundry to collaborate with multiple EDA vendors to create and qualify an interoperable physical verification format that optimizes data delivery and interpretation between physical verification and analysis tools and advanced process technologies.
Problem: Design rules for advanced process technologies are more complex and require detailed and accurate descriptions for correct chip layout creation and post-layout analyses. TSMC collaborates extensively with the EDA partners in the iDRC/iLVS initiative, defines the unified format based on TSMC process requirements, works with EDA partners to implement the new format support in the tools, and closes the loop by qualifying tool accuracy against actual silicon measurements, eliminating data inconsistency, reducing customer tool evaluation time and improving design accuracy.
Solution: TSMC iDRC and iLVS formats unify process design rules specification and technology file generation, simplify data delivery, and ensure data integrity and interpretation. Physical verification and analysis EDA applications, such as DRC and LVS tools, which support iDRC and iLVS formats, will be able to receive accurate design rules data from the iDRC and iLVS files developed and supported by TSMC. The TSMC iDRC/iLVS initiative is supported by major EDA ecosystem partners including Cadence, Magma, Mentor, and Synopsys. The first 40nm iDRC/iLVS was developed in collaboration with TSMC development partners, Mentor and Synopsys, and QA/validation partners, Magma and Cadence. iDRC and iLVS are two of several interoperable EDA interface formats co-developed between TSMC and its design tool partners as part of the TSMC Open Innovation Platform(TM).
Applications: TSMC 40nm process design environment.
Platform: TSMC's AAA initiative is a broad-based program that encompasses all design ecosystem components. It provides accurate standards for all TSMC partners, EDA vendors, IP providers, library developers, and Design Center Alliance (DCA) members. The standards apply to tools, building blocks, and technologies, including TSMC Reference Flow, design for manufacturing (DFM) tools, process design kits (PDK), design support and backend services. The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC's IP, design implementation and DFM capabilities, process technology and backend services.
Availability: The iDRC and iLVS files will be available Q3 2009 in limited release and to selected customers. General release to other customers is targeted for Q4 2009.