Online information source for semiconductor professionals

New Product: Tevet achieves two second per wafer measurement cycle for CVD processes

Popular articles

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

New Product: ASML Brion‚??s Tachyon MB-SRAF enables OPC-like compute times - 19 September 2011

TevetProduct Briefing Outline: Tevet Process Control Technologies has introduced a patent pending parallel sensor Integrated Metrology Module (IMM). The company claims it has best-in-class two second per wafer measurement cycle that is the only production proven IMM that can measure every wafer in the fastest CVD processes.

Problem: As noted in the International Technology Roadmap for Semiconductors Factory Integration section, chamber matching, reliability, processing speed, and single-wafer level tracking and control are among the "factors that impact productivity." With ARC layers, it is critical to control the film thickness to be able to successfully image photoresist in the subsequent lithography step.  A small change in film thickness either locally (uniformity) or globally (across wafer) can result in lithography pattern aberrations that ultimately reduce end-of-line yield.  The high speed of these new generation tools means that standalone metrology tool sampling plans with over an hour between process and measurement would delay detection times of over 150 wafers.  This could result in yield losses running into the hundreds of thousands of dollars per excursion before the conventional metrology-sampling scheme would detect the processing error.

Solution: To eliminate CVD tool downtime due to chamber matching activity, APC loops and out-of-specification processing, fast time-to-detection with the ability to immediately feed back the thickness results is required.  Because of the multiple positions within and between process chambers in the cluster, every wafer measurement is required to control the process performance. Tevet's Trajectory series' integrated metrology is built upon a patent pending parallel sensor architecture.  With multiple sensors positioned in the IMM above the wafer, the Trajectory series IMM can simultaneously measure multiple sites (usually nine; site number and position is configurable) covering more than 100x the wafer area vs. conventional small spot techniques.  The Trajectory series IMM measures and completes calculations within 2 seconds per wafer enabling throughputs of over 300 wph with optimized CVD tool wafer routing sequences and robot speeds.  With no moving parts required for measurement, the Trajectory series IMM provides measurement without reliability risk to the high throughput CVD cluster.  Tevet's proprietary IsTMS algorithms enable measurement in die areas with output of thickness for deposited layers as well as measurement of under-layers in complex stacks.  These data are sent to the CVD tool and the fab HOST computer for dispensation on excursions and for input to APC engines to optimize chamber matching and tighten thickness distribution limits.

Applications: PECVD and CVD for STI and ILD (dual damascene) deposition as well as CMP processes, amongst others.

Platform: Tevet's Integrated Metrology Module is available for use on process tools through BOLTS interface or fully integrated metrology with tools such as Novellus' full line of products including Speed, Vector, ALTUS, and CMP products.

Availability: July 2007 onwards.


Related articles

Nanometrics enters photovoltaics market with acquisition of Tevet - 08 May 2008

Understanding and Improving Wafer Fab Cycle Times - 01 March 2002

New Product: Picarro offers ammonia detection below 1 part-per billion - 22 May 2006

Better Productivity and Faster Cycle Times Through Single- Wafer Processing - 01 June 2000

Best practices for wafer-fab cycle-time management ‚?? tool uptime - 01 June 2004

Reader comments

No comments yet!

Post your comment

Please enter the word you see in the image below: