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New Product: Synopsys’s Yield Explorer identifies and eliminates systematic yield limiters

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A built-in layout viewer makes it easy to correlate any yield relevant information to physical designProduct Briefing Outline: Synopsys has introduced Yield Explorer, a new yield management product that expedites the discovery and mitigation of yield limiters in leading-edge integrated circuits. When compared with traditional methods, Yield Explorer can accelerate the first-silicon debug time by an order of magnitude.

Problem: Traditional yield management methods are centered on wafer and die-level data and do not offer an easy connection to design. These methods are also inadequate for leading- edge technology nodes due to the systematic yield limiters originating in design-process-test interaction. Users have been forced to devise lengthy, manual workarounds to move data between yield management and EDA tools.

Solution: Yield Explorer offers several novel approaches to enable fast interactive analysis for yield engineers dealing with systematic yield limiters. The GUI is uniquely structured around a layout viewer for easy superposition of test failures on the corresponding layers of physical design. In addition to the wide range of analytical functions, users also benefit from the industry standard Tcl scripting environment built into the GUI. This environment can accommodate very large volumes of data with customer-specific data naming and content requirements. Its dynamically extendable data model provides a way of assimilating new types and formats of data without any loss of information or efficiency.

Applications: Rapid diagnosis of yield and performance issues with available fab, test and design data.

Platform: A built-in layout viewer makes it easy to correlate any yield relevant information to physical design, e.g. failing cells to DRC flags or lithographic marginalities. The platform-neutral Analysis Client (Windows, Linux, UNIX) allows all users to use the same application regardless of desktop computing environment.

Availability: March 2009 onwards.

 built-in layout viewer makes it easy to correlate any yield relevant information to physical design, e.g. failing cells to DRC flags or lithographic marginalities.

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