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New Product: Synopsys takes care of strain engineering in DFM

18 October 2006 | By Mark Osborne | Product Briefings > Lithography

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SynopsisProduct Briefing Outline: Synopsys Inc. has introduced a new family of process-aware design-for-manufacturing (PA-DFM) products that analyze variability effects at the custom/analog design stage for 45nm node and below. The PA-DFM product family's core products -- Synopsys Seismos and Paramos - link manufacturing variation information back to design, enabling custom IC (IP, cell, memory and analog) designers to optimize layouts and maximize yields.

Problem: As the 65nm technology node ramps to volume production and the 45nm technology node enters pre-production, IC designers and process engineers need the capability to analyze parametric variations caused by proximity effects, such as the impact of layout on transistor stress state as increasing use of strain engineering in processes is used.

Solution: Together, Seismos and Paramos are designed to address two major sources of variability in IC designs: proximity variations due to stress and other neighborhood effects, and global variations due to the spread of manufacturing process parameters across different die and wafers. By utilizing accurate physical models of the manufacturing process, custom designers can account for manufacturing variability without major changes to the current physical design flow. Seismos is a transistor-level tool for the analysis of stress and other proximity effects in nanometer strained-silicon technologies. As the 65nm technology node ramps to volume production and the 45nm technology node enters pre-production, customers need the capability to analyze parametric variations caused by proximity effects, such as the impact of layout on transistor stress state. Seismos is the first EDA tool to address parametric variations caused by proximity effects. Its models are based on rigorous TCAD simulations validated by silicon data. The tool can easily handle multimillion-transistor designs. Paramos links SPICE models directly to manufacturing conditions by extracting process-aware SPICE compact models that combine calibrated TCAD simulations with global SPICE extraction. It allows customers to simulate the impact of process variability (statistical or systematic) on circuit performance. This methodology provides designers with a physically-based variation model for statistical timing simulations of circuit performance, allowing them to explore designs' sensitivity to real physical process parameters.

Applications: Variability effects at the custom/analog design stage for 45nm and smaller designs.

Platform: Synopsys' DFM product family include the following products: IC Compiler physical design solution; PrimeYield LCC; PrimeYield CMP and PrimeYield CAA technologies; Hercules(TM) physical verification tool; Proteus OPC; CATS(R) mask data preparation product; SiVL(R) lithography verification tool; patented PSM technology; and physics-based TCAD suite of simulation products. Synopsys' Manufacturing Yield Management (MYM) solutions extend directly into the fab, providing customers with real-time access to yield data and the analysis capability needed to reduce random, systematic and parametric defects.


Availability: October 2006 onwards.

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