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New Product: Synopsys Proteus LRC offers 28nm and below lithography verification

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Product Briefing Outline: Synopsys has introduced Proteus LRC for lithography verification at the 2011, SPIE Advanced Lithography conference. Proteus LRC provides comprehensive, process-window-aware checking features to identify locations in a design that are sensitive to process variations, thereby enabling corrective action to be taken prior to committing a design to manufacture. Proteus LRC is integrated into the Proteus Mask Synthesis flow and is targeted for use by OPC and mask data preparation groups at semiconductor manufacturers.

Problem: With the implementation of new manufacturing techniques like extreme ultraviolet lithography (EUV) and double-patterning technology (DPT), the verification process becomes even more challenging. Proteus LRC includes DPT-specific checking functionality that provides error detection for each exposure and mask misalignment condition with a consolidated results viewing environment. As transistor density continues to increase with each new technology node, meeting turn-around-time goals in a production flow becomes more difficult. Effectively meeting this challenge requires efficient use of hardware resources, in addition to advancements in software applications.

Solution: Proteus LRC is designed to deliver the accuracy needed for 28nm and below technology by using optical proximity correction (OPC) models and rigorous first-principle models from embedded Sentaurus Lithography technology. It is imperative for lithography rule check (LRC) tools to accurately predict and verify the critical dimension (CD) variation through the process window to help ensure that adequate process margins are maintained for optimum wafer yield. The Sentaurus Lithography technology embedded in Proteus LRC allows easy access to rigorous first-principle models for resist profiles and topography effects when identifying at-risk hotspots and determining the appropriate course of action.

Applications:
Error detection for each exposure and mask misalignment for EUV and immersion lithography at the 28nm node and below.

Platform: Proteus LRC has been fully integrated in the Proteus Mask Synthesis flow with near-linear scalability to hundreds of standard x86 processor cores, allowing full control over turn-around time and delivering the lowest cost of ownership.

Availability: March 2011 onwards.


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