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New Product: SOLA xT from Novellus incorporates monitoring of ultra-violet thermal process

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Product Briefing Outline: Novellus Systems has introduced its next-generation ultra-violet thermal processing (UVTP) system, the SOLA xT. The SOLA xT is used in the manufacturing of advanced logic devices at 45nm and below and incorporates a proprietary UVTP treatment process that modifies the physical characteristics of a previously-deposited film through exposure to ultraviolet light and heat. The new system, featuring on-board UV monitoring and a customizable optics assembly, provides process flexibility and extendibility over multiple device generations. The first SOLA xT system will be shipped to UMC's Fab 12i in Singapore.

Problem: At 32nm and beyond, ultra-low dielectric constant (ULK) materials must be introduced into the semiconductor manufacturing process flow in order to improve device performance. ULK materials, however, present challenges associated with adhesion and the mechanical properties of the film. Monitoring equipment health and delivering uniform wafer performance is necessary to improve production efficiencies in a high volume manufacturing environment.

Solution: The multi-station sequential processing (MSSP) architecture of SOLA allows independent control of temperature, wavelength and intensity at each station to deliver best-in-class uniformity and productivity. This high degree of process configurability results in UV treated ultra low-k (ULK) films with a 25 percent greater hardness compared to single wavelength, single temperature curing solutions. For example, UVTP is used to remove porogen and improve the mechanical strength of ULK dielectric films used as inter-metal layers. This treatment facilitates device integration and prepares the films to withstand subsequent semiconductor processing steps like packaging and chemical mechanical planarization (CMP). Other advanced manufacturing integration schemes use spin-on dielectrics, which sometimes incur damage during etching, wet cleaning or photoresist ashing steps.

UVTP technology can be used to repair this damage through chemical bond reconstruction. In the front-end-of-the-line, UVTP may also be employed to induce strain in the transistor channel of N-type Metal Oxide Semiconductor (NMOS) devices. Strain is induced by depositing a high tensile stress dielectric film, and subsequently exposing it to UV, resulting in an increase of device performance.

Platform: The multi-station sequential processing architecture of the SOLA platform results in high system throughput and wafer non-uniformity and wafer-to-wafer repeatability.

Availability: January, 2010 onwards.

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