Online information source for semiconductor professionals
New Product: SABRE Excel from Novellus designed to improve plating performance on thin seeds
Popular articles
New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011
Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008
â??Velocityâ?? the new buzzword in Intelâ??s PQS annual awards - 12 April 2012
Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008
New Product: ASML Brionâ??s Tachyon MB-SRAF enables OPC-like compute times - 19 September 2011
Product Briefing Outline: Novellus Systems has launched the
SABRE Excel, an advanced copper electroplating system designed to
provide fill and defect density performance for the 22nm node and
beyond. The platform features a new deposition module incorporating
Novellus’ patented IRISCell technology, as well as new hardware,
software and communications upgrades to the process tool’s mainframe.
Additionally, an advanced plating process has been developed for SABRE
Excel to take advantage of these new features.
Problem: In order to address device reliability concerns at advanced geometries, the industry is trending towards the use of very thin alloy PVD seed layers. While thicker PVD seed layers can cause copper voiding, thinner seed layers result in increased seed resistance, making it difficult to achieve the uniform current density required for consistent feature fill during the initial stages of electrochemical deposition (ECD).
Solution: Novellus’ IRISCell technology eliminates this issue by employing patented field shaping elements that enable dynamic current modulation during the deposition process. Thin PVD seeds also create a challenge for uniform nucleation of the copper film. To address this problem, SABRE Excel’s new plating process, called Multiwave entry, provides millisecond control of the voltage profile during the initial stages of copper deposition.
Applications: PVD seed layers.
Platform: SABRE Excel platform introduces a number of innovative new features targeted at meeting the defect and yield requirements for 22nm. The propensity for ‘killer defects’ has been dramatically reduced using a proprietary, low-corrosion electrolyte. The number of chips per wafer has also been improved by increasing the usable die area through a reduction of the process edge exclusion to only 1mm.
Availability: October 2009 onwards.