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Product Briefing Outline: KLA-Tencor is now offering the latest version of its industry-leading computational lithography tool, ‘PROLITH 11.’ The new tool enables users for the first time to evaluate current double-patterning schemes and cost-effectively explore alternate solutions to lithography challenges in design, materials and process development. This new computational lithography tool also supports single-pass patterning and immersion technologies, according to KLA-Tencor. Problem: Double-patterning lithography (DPL) is a method for constructing the small features of advanced devices by dividing the pattern into two interleaved patterns. This means that a double mask set and new photoresist materials are required for DPL layers, amplifying process complexity and cost. With experts predicting the price of a mask set to exceed $4M at the 32nm node, fabs are strongly motivated to thoroughly characterize how a two-pass, double-mask, dual-resist strategy will print on the wafer under the natural range of process conditions, so that the mask designs, materials and process parameters are right the first time.

Solution: PROLITH 11 allows engineers to model this complex system with unprecedented precision, and then use the model to optimize the system by exploring the effects of small or large changes in mask design, photoresist properties, and scanner or process parameters on the printed pattern. By using PROLITH 11, fabs avoid time-consuming, expensive experiments on product wafers, which delay time-to-market and result in thousands of scrapped processed wafers. PROLITH 11 is claimed to be the only lithography simulator to model the topography specific to double patterning and calculate how variability in printing the first layer could affect the second layer.

Applications: PROLITH 11 models the topography specific to double patterning and calculates how variability in printing the first layer could affect the second layer.

Platform: Complementary to full-chip simulators, which are designed to optimize an entire chip in less than 24 hours, PROLITH models a small area of the die in full detail in a few minutes. While the results of full-chip simulators apply to one set of design and process conditions, PROLITH results can be extrapolated significantly from the conditions under which the model was generated, so that various solutions can be explored. PROLITH results can be used to determine the optimum conditions under which full-chip simulators are run.

Availability: July 2008 onwards.